Liquid crystal display device with high aperture ratio having a metal layer and a storage electrode entirely overlapped with a common electrode

• US 7,515,237 B2
• Filed: 06/27/2005
• Issued: 04/07/2009
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Dong Guk, Park, Seung Ryull
• Primary Examiner(s): Schechter; Andrew
• Assistant Examiner(s): Arendt; Paisley L
• Application Number:
  US11/166,094
• Publication Number:
  US 20060125989A1
• Time in Patent Office: 1,380 Days
• Field of Search: 349/141, 349/38
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

Disclosed is an in-plane switching (IPS) mode liquid crystal display (LCD) device having an increased aperture ratio by overlapping a storage capacitor on a lower end of an electrode. The (IPS) mode liquid crystal display device (LCD) device includes first and second substrates; a gate line and a data line arranged horizontally and vertically to define a plurality of pixel regions on the first substrate; a switching device, having a gate electrode, a semiconductor layer and source and drain electrodes, at a crossing of the gate line and the data line; a passivation film on an entire surface of the first substrate including the switching device; a common electrode and a pixel electrode alternately disposed at an upper portion of the passivation film and generating an in-plane electric field, wherein at least one of the common and pixel electrodes has a first storage capacitor at its lower end; and a liquid crystal layer between the first and second substrates.

Claims

1. An in-plane switching (IPS) mode liquid crystal display(LCD) device, comprising:

first and second substrates;

a plurality of gate lines and data lines arranged horizontally and vertically to define a plurality of pixel regions on the first substrate;

a switching device, having a gate electrode, a semiconductor layer and source and drain electrodes, at each crossing of the gate lines and the data lines;

a passivation film on an entire surface of the first substrate including the switching device;

a common electrode and a pixel electrode arranged in an alternating pattern at an upper portion of the passivation film, wherein the pixel electrode is connected to the drain electrode to generate an in-plane electric field between the common and pixel electrodes by an signal from the drain electrode;

at least one metal layer on a same layer as the gate line; and

at least one first storage electrode on a same layer as the data line and overlapping the metal layer;

a liquid crystal layer between the first and second substrates,

wherein the metal layer and the first storage electrode are disposed below the common electrode so that the metal layer and the first storage electrode are entirely overlapped with the common electrode.

2. The device of claim 1, wherein the metal layer and the first storage electrode have a more narrow width than a width of the common electrode and the pixel electrode.

3. The device of claim 1, further comprising:

a second storage capacitor comprising;

a common line on a same layer as the gate line and receiving a common signal; and

a second storage electrode extending from the drain electrode and overlapping the common line.

4. The device of claim 3, wherein the first storage electrode extends from the second storage electrode.

5. The device of claim 3, further comprising:

a shielding line extending other sides of the common line along outer edges of the pixel region to prevent an influence of a data signal on the pixel electrode.

6. The device of claim 1, further comprising:

a third storage capacitor comprising;

a gate line of a neighboring pixel; and

a third storage electrode electrically connected to the drain electrode and overlapping the gate line.

7. The device of claim 6, wherein the third storage electrode extends from the first storage electrode.

8. The device of claim 1, wherein the common electrode and the pixel electrode are a transparent conductor layer selected from a group consisting of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide) or TO (Tin Oxide).

9. The device of claim 8, wherein the transparent conductor layer extends from the common electrode and is formed at an upper portion of the gate line, the data line and the switching device.

10. The device of claim 1, wherein the common electrode and the pixel electrode are an opaque metal layer.

11. The device of claim 1, further comprising:

a first contact hole electrically connecting the drain electrode or the second storage electrode extending from the drain electrode and one side of the pixel electrode; and

a second contact hole transferring an electrical signal of the common line to the common electrode.

12. The device of claim 11, wherein the second contact hole is formed at a pad terminal part.

13. The device of claim 1, wherein the common electrode and the pixel electrode have bent structure.

14. The device of claim 13, wherein the data line has a bent structure substantially parallel to the common electrode and the pixel electrode.

15. The device of claim 1, wherein the passivation film is one of transparent organic insulation films having a low dielectric constant selected from the group consisting of acrylic resin, BCB (Benzocyclobutene) and a polyimide resin.

16. The device of claim 1, further comprising:

color filters on the second substrate; and

a black matrix at a boundary between the color filters.

17. A method for fabricating an in-plane switching (IPS) mode liquid crystal display (LCD) device, comprising:

preparing first and second substrates;

forming at least one first storage capacitor on the first substrate;

forming a passivation film on the first substrate with at least one storage capacitor formed thereon;

forming a common electrode and a pixel electrode at a region on the passivation film corresponding to the storage capacitor, the pixel electrode being connected to the drain electrode to generate an in-plane electric field between the common and pixel electrodes by an signal from the drain electrode; and

forming a liquid crystal layer between the first and second substrates,

wherein the storage capacitor includes at least one metal layer on a same layer as the gate line and at least one first storage electrode on a same layer as the data line and overlapping the metal layer, the metal layer and the first storage electrode are disposed below the common electrode so that the metal layer and the storage electrode are entirely overlapped with the common electrode.

18. The method of claim 17, wherein forming the at least one storage capacitor comprises:

forming at least one metal layer on the first substrate;

forming a gate insulation film on the first substrate including the at least one metal layer; and

forming a first storage electrode on the gate insulation film.