Integrated memory core and memory interface circuit
First Claim
1. A memory device for use with an external circuit, the memory device comprising:
- at least one first integrated circuit die including,a memory core comprising a plurality of memory cells, anda first interface circuit including a first interface for accessing the memory cells of the memory core and configuring a data rate for transferring data between the memory cells and the first interface circuit; and
at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit.
3 Assignments
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Accused Products
Abstract
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.
531 Citations
27 Claims
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1. A memory device for use with an external circuit, the memory device comprising:
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at least one first integrated circuit die including, a memory core comprising a plurality of memory cells, and a first interface circuit including a first interface for accessing the memory cells of the memory core and configuring a data rate for transferring data between the memory cells and the first interface circuit; and at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit. - View Dependent Claims (2, 3, 5, 13, 14, 15, 16, 17, 18, 19, 27)
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4. A memory device for use with an external circuit. the memory device comprising:
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at least one first integrated circuit die including, a memory core comprising a plurality of memory cells, and a first interface circuit including a first interface for accessing the memory cells of the memory core; at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; a first package housing the at least one first integrated circuit die; and a second package housing the at least one second integrated circuit die.
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6. A memory device for use with an external circuit, the memory device comprising:
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at least one first integrated circuit die including, a memory core comprising a plurality of memory cells, and a first interface circuit including a first interface for accessing the memory cells of the memory core; a plurality of second integrated circuit dies, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; and a single package housing the at least one first integrated circuit die and housing the plurality of second integrated circuit dies.
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7. A memory device for use with an external circuit, the memory device comprising:
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a plurality of first integrated circuit dies including, a memory core comprising a plurality of memory cells, and a first interface circuit including a first interface for accessing the memory cells of the memory core; at least one second integrated circuit die, electrically coupled to the plurality of first integrated circuit dies, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; and a single package housing the plurality of the first integrated circuit dies and housing the at least one second integrated circuit die.
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8. A memory device for use with an external circuit, the memory device comprising:
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a plurality of first integrated circuit dies including, a memory core comprising a plurality of memory cells, and a first interface circuit including a first interface for accessing the memory cells of the memory core; at least one second integrated circuit die. electrically coupled to the plurality of first integrated circuit dies, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; a first package for housing the plurality of the first integrated circuit dies; and a second package for housing the at least one second integrated circuit die.
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9. A memory device for use with an external circuit, the memory device comprising:
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at least one first integrated circuit die including, a memory core comprising a plurality of memory cells, and a first interface circuit including a first interface for accessing the memory cells of the memory core; at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; wherein the second interface of the at least one second integrated circuit die is further for converting protocols between the external circuit and the first interface of the first integrated circuit die. - View Dependent Claims (10, 11, 12, 25, 26)
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20. A memory device for use with an external circuit, the memory device comprising:
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a first integrated circuit die including, a memory core including a plurality of memory cells, and a first interface circuit having a first interface and coupled to the memory cells, for dynamically configuring an internal data rate for transferring data between the memory cells and the first interface circuit; and a second integrated circuit die, electrically coupled to the first integrated circuit die, including a second interface for accessing data from the memory core via the first interface circuit and for interfacing said memory core to the external circuit. - View Dependent Claims (21, 22, 23, 24)
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Specification