Current driven memory cells having enhanced current and enhanced current symmetry

• US 7,515,457 B2
• Filed: 02/24/2006
• Issued: 04/07/2009
• Est. Priority Date: 02/24/2006
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Chen, Eugene Youjun, Huai, Yiming
• Primary Examiner(s): Hoang; Huan
• Assistant Examiner(s): TRAN, ANTHAN
• Application Number:
  US11/361,267
• Publication Number:
  US 20080205121A1
• Time in Patent Office: 1,138 Days
• Field of Search: 365/158
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing

Abstract

A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on.

Claims

1. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction;

voltage supply for the magnetic memory, the voltage supply providing a supply voltage;

a voltage pump coupled with the plurality of magnetic storage cells and the voltage supply, the voltage pump for providing a bias voltage to the selection device, the bias voltage having a magnitude greater than the supply voltage, the bias voltage allowing the selection device to support the first write current and the second write current, the first and second write current capable of programming the magnetic element; and

control logic coupled with the plurality of magnetic storage cells, the control logic for ensuring that the bias voltage is provided to the selection device only when the first write current or the second write current is provided to the magnetic element.

2. The magnetic memory of claim 1 wherein the voltage pump includes at least one charge pump.

3. The magnetic memory of claim 2 wherein the at least one charge pump further includes at least one doubler.

4. The magnetic memory of claim 2 wherein the at least one charge pump further includes at least one inverter.

5. The magnetic memory of claim 2 further comprising:

at least one voltage splitter coupled with the at least one charge pump and the plurality of magnetic storage cells, the voltage splitter for providing a plurality of voltages to the selection device, the plurality of voltages having a maximum magnitude greater than the supply voltage.

6. The magnetic memory of claim 2 wherein the selection device includes a transistor having a gate and wherein the bias voltage is provided to the gate.

7. The magnetic memory of claim 1 wherein the magnetic element is configured to be programmed using spin transfer.

8. The magnetic memory of claim 1 wherein the selection device is a selection transistor having a gate oxide, the gate oxide having a thickness of at least 0.8 nm.

9. The magnetic memory of claim 1 wherein the selection device is a selection transistor having a gate oxide, the gate oxide having a thickness of at least 1.2 nm.

10. The magnetic memory of claim 1 wherein the selection device is a selection transistor having a gate insulator having a dielectric constant of at least six.

11. A resistive memory comprising:

at least one resistive storage cell, each of the at least one resistive storage cell including a resistive element and a selection device coupled with the resistive element, the resistive element being programmed by a write current driven through the resistive element, a resistance of the resistive element indicating a state of the resistive element and data stored in the resistive element;

voltage supply for the resistive memory, the voltage supply providing a supply voltage;

a voltage pump coupled with the plurality of resistive storage cells and the voltage supply, the voltage pump for providing a bias voltage, the bias voltage having a magnitude greater than the supply voltage, the bias voltage allowing the selection device to support the write current capable of programming the magnetic element;

control logic coupled with the plurality of resistive storage cells, the control logic for ensuring that the bias voltage is provided to the selection device only when the write current is provided to the resistive storage element.

12. A method for utilizing a magnetic memory including a plurality of magnetic storage cells and a voltage supply, each of the plurality of magnetic storage cells including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction, the voltage supply providing a supply voltage, the method comprising:

driving the first current or the second current through the magnetic element in a portion of the plurality of magnetic storage cells; and

providing a bias voltage to the selection device of the portion of the plurality of magnetic storage cells while the first current or the second current is driven through the magnetic element, the bias voltage having a magnitude greater than the supply voltage, the bias voltage allowing the selection device to support the first write current and the second write current, the first and second write current capable of programming the magnetic element, wherein the step of providing the bias voltage further includes

utilizing control logic to ensure that the bias voltage is provided to the selection device only when the first write current or the second write current is provided to the magnetic element.

13. The method of claim 12 wherein the selection device includes a transistor having a gate and wherein the bias voltage providing further includes:

providing the bias voltage to the gate.

14. The method of claim 12 wherein the magnetic element is configured to be programmed using spin transfer.

15. A method for utilizing a magnetic memory including a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction, the voltage supply providing a supply voltage, the method comprising:

driving the first current or the second current through the magnetic element in a portion of the plurality of magnetic storage cells; and

providing a bias voltage to the selection device of the portion of the plurality of magnetic storage cells while the first current or the second current is driven through the magnetic element, the bias voltage having a magnitude greater than 1.2 volts, the bias voltage allowing the selection device to support the first write current and the second write current, the first and second write current capable of programming the magnetic element;

wherein the step of providing the bias voltage further includes;

utilizing control logic to ensure that the bias voltage is to the selection device only when the first write current or the second write current is provided to the magnetic element.

16. The method of claim 15 wherein the magnitude of the bias voltage is greater than 1.5 volts.

17. The method of claim 15 wherein the magnitude of the bias voltage is greater than 5 volts.

18. The method of claim 15 wherein the magnetic element is configured to be programmed using spin transfer.