Structure and access method for magnetic memory cell and circuit of magnetic memory

• US 7,515,458 B2
• Filed: 08/18/2006
• Issued: 04/07/2009
• Est. Priority Date: 04/18/2006
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Kao, Ming-Jer, Chen, Yung-Hsiang, Lee, Yuan-Jen, Wang, Yung-Hung, Hung, Chien-Chung
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Graham; Kretelia
• Application Number:
  US11/465,460
• Publication Number:
  US 20070242501A1
• Time in Patent Office: 963 Days
• Field of Search: 365/158
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

A magnetic memory cell, used in a magnetic memory device, includes a stacked magnetic pinned layer, serving as a part of the base structure. The stacked magnetic pinned stacked layer has a top pinned layer and a bottom pinned layer, between which there is a sufficient large magnetic coupling force to maintain magnetization of the top pinned layer on a reference direction. A tunnel barrier layer is disposed on the stacked magnetic pinned layer. A magnetic free stacked layer is disposed on the tunnel barrier layer. The magnetic free stacked layer includes a bottom free layer having a bottom magnetization and a top free layer having a top magnetization. When no assisted magnetic field is applied, the bottom magnetization is anti-parallel to the top magnetization and is perpendicular to the reference direction on the top pinned layer. A magnetic bias layer can be also disposed on the top free layer.

Claims

1. A magnetic memory cell structure, comprising:

a stacked magnetic pinned layer, comprising a top pinned layer and a bottom pinned layer, there being a sufficient large magnetic coupling force between the top pinned layer and the bottom pinned layer for maintaining a magnetization vector of the top pinned layer in a reference direction;

a tunnel barrier layer, disposed on the stacked magnetic pinned layer; and

a magnetic free stacked layer, disposed on the tunnel barrier layer, wherein the magnetic free stacked layer comprises a bottom free layer having a bottom magnetization vector and a top free layer having a top magnetization vector,

wherein if no assisted magnetic field is supplied, the bottom magnetization vector is anti-parallel to the top magnetization vector and is perpendicular to the reference direction of the top pinned layer.

2. The magnetic memory cell structure as claimed in claim 1 further comprising a magnetic bias layer disposed on the magnetic free stacked layer, wherein the magnetic bias layer produces a biased magnetic field vector to the magnetic free stacked layer for shifting a writing area to a magnetic field zero.

3. The magnetic memory cell structure as claimed in claim 2, wherein the biased magnetic field vector is parallel or anti-parallel to the top magnetization vector of the top free layer.

4. The magnetic memory cell structure as claimed in claim 2, wherein the magnetic bias layer is a magnetic single layer.

5. The magnetic memory cell structure as claimed in claim 2, wherein the magnetic bias layer has a magnetization vector to produce the biased magnetic field vector.

6. The magnetic memory cell structure as claimed in claim 1, wherein the top free layer and the bottom free layer of the magnetic free stacked layer comprise ferromagnetic metal material and are separated by a magnetic coupling spacer.

7. A data access method, suitable for a magnetic memory cell of a magnetic memory device, wherein the magnetic memory device comprises the magnetic memory cell structure as claimed in claim 1, a word current line, and a bit current line, wherein the direction of an easy axis of the magnetic free stacked layer is defined as 0°

, the data access method comprising;

a first reading stage, comprising;

supplying a first assisted magnetic field in a first direction to the magnetic memory cell;

supplying a second assisted magnetic field in a second direction to the magnetic memory cell, wherein a total magnetic field direction of the first and the second directions is on the easy axis, wherein the actions of the first and the second directions change the direction of the bottom magnetization vector of the magnetic free stacked layer to be parallel or anti-parallel to the direction of the magnetization vector of the top pinned layer; and

reading a magnetoresistance of the magnetic memory cell, obtaining a binary data presently stored after comparing the magnetoresistance and a reference magnetoresistance;

a second reading stage, comprising turning off the second assisted magnetic field; and

a third reading stage, turning off the first assisted magnetic field.

8. The data access method as claimed in claim 7, wherein the first reading stage further comprises supplying a predetermined negative direction magnetic field which is in opposite direction to the second assisted magnetic field before supplying the second assisted magnetic field and during the period before supplying the first assisted magnetic field.

9. The data access method as claimed in claim 8, wherein the second and the third reading stages further comprise supplying another successive negative direction magnetic field which is in opposite direction to the second assisted magnetic field after turning off the second assisted magnetic field and during the period after turning off the first assisted magnetic field.

10. The data access method as claimed in claim 7, wherein the second and the third reading stages further comprise supplying a successive negative direction magnetic field which is in opposite direction to the second assisted magnetic field after turning off the second assisted magnetic field and during the period after turning off the first assisted magnetic field.

11. The data access method as claimed in claim 7 further comprising:

a first writing stage, executing the same steps as in the first reading stage, wherein the process is finished after executing the second and the third reading stages if the binary data is the same as a data to be written;

a second writing stage, turning off the first assisted magnetic field if the binary data being different from a data to be written; and

a third writing stage, turning off the second assisted magnetic field if the binary data being different from a data to be written.

12. The data access method as claimed in claim 11, wherein the first writing stage further comprises supplying a predetermined negative direction magnetic field which is in opposite direction to the second assisted magnetic field before supplying the second assisted magnetic field and during the period before supplying the first assisted magnetic field.

13. The data access method as claimed in claim 12, wherein the second and the third writing stages further comprise supplying another successive negative direction magnetic field which is in opposite direction to the first assisted magnetic field after turning off the first assisted magnetic field and during the period after turning off the second assisted magnetic field.

14. The data access method as claimed in claim 11, wherein the second and the third writing stages further comprise supplying a successive negative direction magnetic field which is in opposite direction to the first assisted magnetic field after turning off the first assisted magnetic field and during the period after turning off the second assisted magnetic field.

15. The data access method as claimed in claim 11, wherein during the third writing stage, the magnetization vector of the magnetic free stacked layer is rotated 180°

.

16. The data access method as claimed in claim 7, wherein during the first reading stage, the first direction of the first assisted magnetic field is substantially in 90°

to the second direction of the second assisted magnetic field.

17. The data access method as claimed in claim 16, wherein during the first reading stage, the first direction is substantially at 45°

, 135°

, 225°

, or 315°

to the easy axis.

18. A magnetic memory circuit, comprising:

a plurality of magnetic memory cell structures as claimed in claim 1, forming a memory cell array having a plurality of memory columns and a plurality of memory rows;

a plurality of bit current lines, disposed respectively corresponding to the memory columns;

a plurality of word current lines, disposed respectively corresponding to the memory rows;

a plurality of read bit lines, each of the read bit lines respectively reading a magnetoresistance of each of the memory cell structures;

a driving circuit unit, controlling the word current lines, the bit current lines, and the read bit lines, so as to supply a plurality of assisted magnetic fields required for data access to the selected memory cell structure and to read the magnetoresistance of the selected memory cell structure, wherein one of the memory cell structures not being supplied with magnetic fields is serving as a reference memory cell, and a reference magnetoresistance of the reference memory cell is read; and

a comparison circuit unit, receiving the magnetoresistance and comparing the received magnetoresistance with the reference magnetoresistance to determine a binary data stored in the selected memory cell.

19. The magnetic memory circuit as claimed in claim 18, wherein a reference memory row is further disposed at one side of the memory rows so that the outmost memory row can be compared with the reference memory row.

20. The magnetic memory circuit as claimed in claim 18, wherein the direction of an easy axis of the magnetic free stacked layer is defined as 0°

, a positive direction current passing through the word current lines produces a magnetic field in the direction of +45°

, a positive direction current passing through the bit current lines produces a magnetic field in the direction of −

45°

, wherein a data access to the selected memory cell structure in the magnetic memory circuit comprises;

a first reading stage, comprising;

supplying a first assisted magnetic field to the magnetic memory cell, the first assisted magnetic field being substantially in a first direction at 45°

, 135°

, 225°

, or 315°

to the easy axis;

supplying a second assisted magnetic field to the magnetic memory cell, wherein a second direction of the second assisted magnetic field is substantially at 90°

to the first direction, so that a total magnetic field direction is substantially on the easy axis; and

reading a magnetoresistance of the magnetic memory cell, a presently stored binary data could be obtained after comparing the magnetoresistance and a reference magnetoresistance;

a second reading stage, comprising turning off the second assisted magnetic field; and

a third reading stage, turning off the first assisted magnetic field.

21. The magnetic memory circuit as claimed in claim 20, wherein the first reading stage further comprises supplying a predetermined negative direction magnetic field which is in opposite direction to the second assisted magnetic field before supplying the second assisted magnetic field and during the period before supplying the first assisted magnetic field.

22. The magnetic memory circuit as claimed in claim 20, wherein the second and the third reading stages further comprise supplying a successive negative direction magnetic field which is in opposite direction to the second assisted magnetic field after turning off the second assisted magnetic field and during the period after turning off the first assisted magnetic field.

23. The magnetic memory circuit as claimed in claim 20 further comprising:

a first writing stage, executing the same steps as in the first reading stage, wherein the process is finished after executing the second and the third reading stages if the binary data is the same as a data to be written;

a second writing stage, turning off the first assisted magnetic field if the binary data is different from a data to be written; and

a third writing stage, turning off the second assisted magnetic field if the binary data is different from a data to be written.

24. The magnetic memory circuit as claimed in claim 23, wherein the first writing stage further comprises supplying a predetermined negative direction magnetic field which is in opposite direction to the second assisted magnetic field before supplying the second assisted magnetic field and during the period before supplying the first assisted magnetic field.

25. The magnetic memory circuit as claimed in claim 23, wherein the second and the third writing stages further comprise supplying a successive negative direction magnetic field which is in opposite direction to the first assisted magnetic field after turning off the first assisted magnetic field and during the period after turning off the second assisted magnetic field.

26. The magnetic memory circuit as claimed in claim 18, wherein the reference memory cell and the selected memory cell structure are in adjacent diagonal relationship.

27. A magnetic memory circuit, comprising:

a plurality of memory cell structures, forming a memory cell array having a plurality of memory columns and a plurality of memory rows;

a plurality of bit current lines, disposed respectively corresponding to the memory columns;

a plurality of word current lines, disposed respectively corresponding to the memory rows;

a plurality of read bit lines, each of the read bit lines reading a magnetoresistance of each of the memory cell structures;

a driving circuit unit, controlling the word current lines, the bit current lines, and the read bit lines to directly read the magnetoresistance of the selected memory cell structure, to supply a plurality of assisted magnetic fields required for data access to a reference memory cell structure and to read a reference magnetoresistance, wherein one of the memory cell structures different from the selected memory cell structure serves as the reference memory cell structure; and

a comparison circuit unit, receiving the magnetoresistance and comparing the received magnetoresistance with the reference magnetoresistance to determine a binary data stored in the selected memory cell structures,

wherein during a writing operation, the binary data read by the comparison circuit unit is kept if the binary data is the same as a data to be written, the direction of a magnetization vector of a magnetic free stacked layer of the selected memory cell structure is reversed by the driving circuit unit if the binary data is different from the data to be written.

28. The magnetic memory circuit as claimed in claim 27, wherein the reference memory cell and the selected memory cell structure are in adjacent diagonal relationship.