Memory with output control

• US 7,515,471 B2
• Filed: 10/19/2006
• Issued: 04/07/2009
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Oh, HakJune, Pyeon, Hong Beom
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/583,354
• Publication Number:
  US 20070153576A1
• Time in Patent Office: 901 Days
• Field of Search: 365/185.11, 365/185.18, 365/185.33, 365/219, 365/220, 365/221
• US Class Current: 365/185.11
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A semiconductor memory device comprising:

memory;

a serial data link interface configured to receive serial input data at a serial data input port, and to transfer serial data to a serial data output port;

a control input port for receiving a first output enable signal that is used to enable the memory device to transfer the serial data to the serial data output port;

a control output port for outputting a second output enable signal, and

control circuitry responsive to the first output enable signal that controls data transfer on the serial data output port.

2. The semiconductor memory device of claim 1 further comprising a second control input port for receiving an input enable signal that is used to enable the memory device to receive the serial input data, the control input port being a first control input port.

3. The semiconductor memory device of claim 2 further comprising a second control output port for outputting a second input enable signal, the input enable signal corresponding to a first input enable signal.

4. The semiconductor memory device of claim 1 further comprising a clock input for receiving a clock signal.

5. The semiconductor memory device of claim 4, further including a clock output for providing an output clock signal corresponding to the clock signal.

6. The semiconductor memory device of claim 5, further including delay adjustment circuitry for synchronize any phase difference between the clock signal and the output clock signal.

7. The semiconductor memory device of claim 6, wherein the delay adjustment circuitry includes one of a delay locked loop and a phase locked loop.

8. The semiconductor memory device of claim 1, wherein the memory comprises a plurality of memory banks.

9. The semiconductor memory device of claim 1, wherein the second output enable signal is the first output enable signal delayed.

10. The semiconductor memory device of claim 1, wherein the second output enable signal is derived from the first output enable signal.

11. The semiconductor memory device of claim 1, wherein the serial data link interface is further configured to convert serial input data into parallel data and transfer the data to the memory.

12. The semiconductor memory device of claim 1, wherein the serial data link interface is further configured to transfer data from the memory into serial output data.

13. The semiconductor memory device of claim 12, wherein the serial data link interface is further configured to convert serial input data into parallel data and parallel data into serial output data.

14. The semiconductor memory device of claim 1 further comprising a unique device identification number.

15. The semiconductor memory device of claim 14, wherein the control circuitry controls access to the memory in response to a target device address corresponding to the unique device identification number associated with the device, the target device address being contained in a target device address field of the serial input data.

16. The semiconductor memory device of claim 15, wherein the control circuitry controls the transfer of the data from a location in the memory identified in an address field of the serial input data.

17. The semiconductor memory device of claim 1, wherein the memory, the serial data link interface and the control circuitry are located within a single package having a one-side pad architecture.

18. The semiconductor memory device of claim 1, wherein the memory comprises a non-volatile memory bank.

19. The semiconductor memory device of claim 18, wherein the non-volatile memory bank is a flash memory bank.

20. The semiconductor memory device of claim 19, wherein the non-volatile memory bank is a NAND flash memory bank.

21. The semiconductor memory device of claim 1, wherein control circuitry is further responsive to a clock signal to control data transfer on the serial data output port.

22. The semiconductor memory device of claim 1, wherein the control circuitry is further configured to require an output enable signal to remain active until the data transfer on the serial output port is completed.

23. The semiconductor memory device of claim 1, wherein the serial data link interface includes circuits for passing the serial input data received at the serial data input port to the serial data output port.

24. The semiconductor memory device of claim 23, wherein the circuits include

an input buffer for providing buffered serial input data corresponding to the serial input data,

an output driver for driving one of the buffered serial input data and the serial data onto the serial data output port,

a multiplexor for selectively providing one of the buffered serial input data and the serial data to the output driver,

a clocking circuit for coupling the buffered serial input data to the multiplexor.

25. A semiconductor memory device comprising:

memory;

a serial data link interface configured to receive serial input data at a serial data input port, and to transfer serial data to a serial data output port;

a first control input port for receiving a first output enable signal that is used to enable the memory device to transfer the serial data to the serial data output port;

a second control input port for receiving an input enable signal that is used to enable the memory device to receive the serial input data;

a control output port for outputting a second output enable signal,

a clock input port for receiving a clock signal; and

control circuitry responsive to the output enable signal that controls data transfer on the serial data output port and to the input enable signal that enables the device to receive the serial input data.

26. The semiconductor memory device of claim 25, wherein the first control input port, the second control input port, the control output port, the serial data input port, and the serial data output port are configured to be synchronized with the clock signal.

27. The semiconductor memory device of claim 26, wherein the first control input port, the second control input port, the control output port, the serial data input port, and the serial data output port are configured to be synchronized at a double data rate with the rising and falling edges of clock signal.

28. The semiconductor memory device of claim 25, wherein the control circuitry is further responsive to the clock signal to enable the device to receive the serial input data.

29. The semiconductor memory device of claim 25, wherein the control circuitry is configured to require an input enable signal to remain active until a target device address and a command instruction is received.

30. The semiconductor memory device of claim 29, wherein the control circuitry is further configured to require an input enable signal to remain active until a row address is received.

31. The semiconductor memory device of claim 29, wherein the control circuitry is further configured to require an input enable signal to remain active until a column address is received.

32. The semiconductor memory device of claim 29, wherein the control circuitry is further configured to require an input enable signal to remain active until a row address instruction, a column address, and data is received.

33. The semiconductor memory device of claim 25, wherein the second output enable signal is derived from the first output enable signal.

34. A method of controlling data transfer from a serial data link interface in a semiconductor memory device, the method comprising:

receiving an instruction at a serial data input port;

receiving an output enable signal at a control input port;

enabling output of serial output data based on the output enable signal; and

sending a serial output data stream from the serial data link interface.

35. The method of claim 34, wherein the method further comprises:

transferring parallel data between the memory and the serial data link interface; and

converting the parallel data into serial output data prior to sending the serial output data stream from the serial data link interface.

36. The method of claim 34, wherein the semiconductor memory device is a flash memory device.

37. The method of claim 34, wherein the flash memory device is a NAND device.

38. A flash memory system comprising:

a first flash memory device having

a serial data in put port for receiving serial input data,

a serial data output port for providing serial output data,

a control input port for receiving a first output enable signal from an external source device,

a control output port for providing a second output enable signal, the first flash memory device configured to provide the serial output data based on the first output enable signal; and

a second flash memory device serially connected to the first flash memory device, and having a serial data input port configured to receive the serial output data from the first flash memory device.

39. The flash memory system of claim 38 wherein:

the second flash memory device further includes a serial data output port configured for providing the serial output data and a control input port configured for receiving the second output enable signal from the control output port of the first flash memory device.

40. The flash memory system of claim 39, wherein the second output enable signal is the first input signal delayed.

41. The flash memory system of claim 39, wherein the second output enable signal is derived from the first output enable signal.

42. The flash memory system of claim 39, wherein the second flash memory device further includes a control output port for providing a third output enable signal to an external target device.

43. The flash memory system of claim 38, wherein the external source device is a controller.

44. The flash memory system of claim 38, wherein the external source device is a flash memory device.

45. The flash memory system of claim 38, wherein:

the first flash memory device further includes

a second control input port for receiving a first input enable signal from the external source device, the control input port being a first control input port, and

a second control output port for providing a second input enable signal, the control output port being a first control output port; and

the second flash memory device further includes a control input port for receiving the second input enable signal from the first flash memory device.

46. The flash memory system of claim 38, wherein a single clock signal is communicated in a cascading signal to each flash memory device of the plurality of serially connected flash memory devices.

47. The flash memory system of claim 38, wherein each of the plurality of flash memory devices further include

a flash memory bank;

a serial data link interface configured to receive the serial input data at the serial data input port and for transferring the serial input data to the flash memory bank, and to transfer the serial output data to the serial data output port; and

control circuitry that controls data transfer between the serial data link interface and the flash memory bank, and between the serial data link interface and the serial data output port.

48. The flash memory system of 47, wherein the flash memory bank is a NAND flash memory.