Memory array peripheral structures and use

• US 7,515,502 B1
• Filed: 09/18/2007
• Issued: 04/07/2009
• Est. Priority Date: 09/18/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis Lu-Chen, Ouyang, Xu, Ahsan, Ishtiaq
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US11/856,964
• Publication Number:
  US 20090073796A1
• Time in Patent Office: 567 Days
• Field of Search: 365/230.03, 365/210, 365/225.7, 365/63
• US Class Current: 365/230.03
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/816 for an application-specific layout
• CPC Class Codes: G11C 29/838 with substitution of defective spares
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.

Claims

1. A method comprising:

fabricating a memory array comprising one or more memory blocks, each memory block of said one or more memory blocks comprising memory cells arranged in rows and columns;

for each memory block of said one or more memory blocks, designating memory cells in one or more adjacent rings of memory cells nearest a perimeter of said memory block as dummy memory cells;

selecting a set of one to all of said one or more memory blocks to create a set of selected memory blocks;

for each memory block of said set of selected memory blocks and before a final fabrication level of said memory array, electrically connecting dummy memory cells of selected rows together, electrically connecting dummy memory cells of selected columns together or both electrically connecting dummy memory cells of selected rows together and electrically connecting dummy memory cells of selected columns together;

for each memory block of said of said set of selected memory blocks and before said final fabrication level, testing said selected rows, selected columns or selected rows and columns of dummy memory cells of said;

for each memory block of said of said set of selected memory blocks and after said testing, completing fabrication of said memory block to said final fabrication level;

for each memory block of said of said set of selected memory blocks, connecting said dummy cells at opposite ends of said selected rows of dummy memory cells to normally fabricated first pads of said memory array;

for each memory block of said set of selected memory blocks, connecting dummy cells at opposites ends of said selected columns of dummy memory cells to normally fabricated second pads of said memory array of said memory array;

forming a fuse between one or more of said first pads and said selected rows of dummy memory cells;

forming a fuse between one or more of said second pads and said selected rows of dummy memory cells;

for each memory block of said one or more memory blocks, except for dummy memory cells, electrically connecting each memory cell in each row of said memory array to a respective wordline and each wordline to a respective wordline driver;

for each memory block of said one or more memory blocks except for dummy memory cells, electrically connecting each memory cell in each column of said memory array to a respective bitline and each bitline to a respective bitline decoder;

wherein said selected rows, selected columns or selected rows and columns of dummy memory cells are rows, columns or rows and columns along said perimeter of said memory blocks of said set of selected memory blocks; and

wherein said memory cells are selected from the group consisting of static random access memory cells and dynamic access memory cells.

2. A method comprising:

fabricating a memory array comprising an array of one or more memory blocks, each memory block of said one or more memory blocks comprising an array of memory cells arranged in rows and columns;

for each memory block of said one or more memory blocks, designating memory cells in one or more adjacent rings of memory cells nearest a perimeter of said memory block as dummy memory cells;

selecting a set of one to all of said one or more memory blocks to create a set of selected memory blocks;

for each memory block of said one or more memory blocks, except for dummy memory cells, electrically connecting each memory cell in each row to a respective wordline and each wordline to a respective wordline driver;

for each memory block of said one or more memory blocks, except for dummy memory cells, electrically connecting each memory cell in each column to a respective bitline and each bitline to a respective bitline decoder;

for each memory block of said set of selected memory blocks, electrically connecting a selected row or column of said dummy memory cells together and to selected pads of said memory array;

applying a voltage at a first level to said selected pads;

for each memory block of said one or more memory blocks, selecting a wordline or bitline that is adjacent to said selected row or column and applying a voltage at a second level to said selected wordline or bitline, said first level different from said second level;

for each memory block of said set of selected memory blocks, measuring any current flow between said selected pads and said selected wordline or bitline;

connecting said selected pads to a terminal ground pad or a terminal power pad of an integrated circuit chip containing said memory array;

for each memory block of said set of selected memory blocks, (i) forming a fuse between one or more of said first pads and said selected row of dummy memory cells;

or (ii) forming a fuse between one or more of said second pads and said selected row of dummy memory cells; and

wherein said memory cells are selected from the group consisting of static random access memory cells and dynamic access memory cells.

3. A memory array comprising:

an array of one or more memory blocks, each memory block comprising an array of memory cells arranged in rows and columns, memory cells in one or more adjacent rings of memory cells nearest a perimeter of each memory block of said one or more memory blocks designated as dummy memory cells;

for at least one of said one or more memory blocks, dummy memory cells in a row or column electrically connected together into a dummy row or dummy column, a first end of said dummy row or dummy column connected to a first pad of said memory array;

for each memory block of said one or more memory blocks, except for dummy memory cells, memory cells in each row connected to a respective wordline and each wordline connected to a respective wordline driver;

for each memory block of said one or more memory blocks, except for dummy memory cells, memory cells in each column of said memory array connected to a respective bitline and each bitline connected to a respective bitline decoder;

a second end of said dummy row or dummy column connected to a second pad of said memory array;

a fuse between said row or column of said dummy memory cells and said first pad;

for each memory block of said one or more memory blocks, all dummy memory cells in each row of dummy memory cells connected to respective dummy wordlines and each dummy wordline of said dummy wordlines connected to a respective dummy wordline driver;

for each memory block of said one or more memory blocks, all dummy memory cells in each column of dummy memory cells connected to respective dummy bitlines and each dummy bitline of said dummy bitlines connected to a respective dummy bitline decoder;

for each memory block of said one or more memory blocks, all dummy wordline drivers and all dummy bitline decoders connected to a redundant wordline/bitline control circuit;

wherein said first and second pads are both connected to terminal ground pads or both connected to terminal power pads of an integrated circuit chip containing said memory array; and

wherein said memory cells are selected from the group consisting of static random access memory cells and dynamic access memory cells.