Apparatus, methods and articles of manufacture for a multi-band switch

• US 7,515,882 B2
• Filed: 12/16/2003
• Issued: 04/07/2009
• Est. Priority Date: 12/17/2002
• Status: Expired due to Fees

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: MACOM Technology Solutions Holdings, Inc.
• Inventors: Kelcourse, Mark F., Brindle, Christopher N.
• Primary Examiner(s): Anderson; Matthew D
• Assistant Examiner(s): GONZALES, APRIL GUZMAN
• Application Number:
  US10/737,375
• Publication Number:
  US 20040141470A1
• Time in Patent Office: 1,939 Days
• Field of Search: 455/78, 455/82, 455/101, 455/121, 333/103, 333/101, 330/51, 330/151, 330/86
• US Class Current: 455/78
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/0057 using diplexing or multiplexing filters for selecting the desired band
• CPC Class Codes: H04B 1/006 using switches for selecting the desired band H04B1/0057 takes precedence
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

The invention is directed to a multi-band switch having a transmitter switching section with a plurality of transmission ports, and a receiver switching section with a plurality of receiver ports, each having associated switching topologies to switch one of the ports to an antenna port. The switching topologies may use a plurality of series-connected FETs, such as insulated gate n-channel FETs, where the transmitter port switching elements may have larger switching transistors than the receiver port switching elements. The main signal path transistors of the transmitter and receiver switching elements be interdigitated FETs, in which source region fingers and drain region fingers alternate within the transistor area. These interdigitated source and drain regions may be spaced apart from each other by a sinuous channel region, over which is a gate metallization.

Claims

1. A single-die integrated circuit for switching among a plurality of transmission ports and a plurality of received reports, comprising:

a transmitter switching section having a plurality of transmission ports, said transmitter switching section operable to switch a selected one of the plurality of transmission ports to a transmission node wherein, for each transmission port, the transmission switching section includes a plurality of FETs having current paths coupled in series with each other and operable to couple the transmission port to the transmission node, wherein a first one of the FETs proximate the respective transmission port has a current path with a first end coupled to the transmission port and a gate;

a first feed-forward capacitor coupled between said first end of said current path and said gate of said first one of the FETs; and

a receiver switching section having a plurality of received ports, said receiver switching section operable to switch a selected one of the plurality of received reports to the transmission node.

2. The integrated circuit of claim 1, wherein the receiver switching section includes at least two cascaded stages, a first cascaded stage controllable to switch the transmission node to a receiver node, a second cascaded stage controllable to switch the receiver node to a selected one of the plurality of receiver ports.

3. The integrated circuit of claim 1, and further comprising an antenna port coupled to the transmission node.

4. The integrated circuit of claim 1, wherein at least one of the FET switching topologies includes at least one FET having a plurality of contiguous source regions interdigitated with a plurality of contiguous drain regions, a sinuous gate formed to wind between the source regions and the drain regions.

5. The integrated circuit of claim 1 wherein the plurality of FETs further comprises a last one of the FETs proximate the transmission node and having a current path with a first and coupled to the transmission node, the integrated circuit further comprising a second feed-forward capacitor coupled from gate to the first end of said current path of said last one of the FETs.

6. no The integrated circuit of claim 5, further comprising, in each transmitter switching section, a bypass resistor coupled in parallel with the current paths of the plurality of FETs in series.

7. The integrated circuit of claim 1, further comprising, in each transmitter switching section, a bypass resistor coupled in parallel with the current paths of the plurality of FETs in series.

8. A single-die multiband switch for wireless communication, comprising:

an antenna port;

a plurality of transmitter ports, for each transmitter port a switching topology operable to switch the transmitter port to the antenna port; and

a plurality of received ports,

a switching topology operable to switch a selected one of said receiver ports to the antenna port, said switching topologies comprising a multiple-stage switching circuit, a first stage of the multiple-stage switching circuit selectively connecting or isolating the antenna port from the multiple-stage switching topology, and a last stage of the multiple-stage switching topology selectively connecting or isolating a plurality of the receiver ports from the multi-stage switching topology, wherein said last stage includes, for each receiver port, a signal path FET having a current path controllable to connect the receiver port to an intermediate node, said first stage operable to connect the intermediate node to the antenna port, and wherein each said signal path FET has a gate to which a control signal is applied, a shunt FET having a drain coupled to the gate of the signal path FET, a source coupled to ground, and operable to enhance isolation of the receiver port from the intermediate node when the signal path FET is in and OFF state.

9. The switch of claim 8, wherein said first stage of said switching topology comprises a plurality of series-connected field effect transistors, wherein a control signal for said switching topology controls said switching topology to selectively connect or isolate a respective transmitter or receiver port from the antenna port.

10. The switch of claim 8, wherein at least one of the switching topologies comprises at least one interdigitated field effect transistor having a plurality of elongated contiguous drain regions, a plurality of elongated contiguous source regions interdigitated with the drain regions, an elongated sinuous channel region spacing apart the drain regions from the source regions, and a gate overlying the channel region to switch the interdigitated field effect transistor between an ON and an OFF state.

11. The switch of claim 8, wherein the die has an area, the transmitter port switching topologies occupying an area on the die which is substantially larger than the receiver port switching topologies.

12. A method of switching one of a plurality of transmitters and a plurality of receivers to a transmitter/receiver antenna, comprising the steps of:

connecting each transmitter to a respective one of the plurality of transmitter ports formed on a single integrated circuit die;

connecting each receiver to a respective one of a plurality of received reports formed on the die;

controlling a selected one of a plurality of switching topologies, each associated with a respective one of the transmitter and receiver ports, to connect a respective selected one of the transmitter and receiver ports to an antenna port formed on the die; and

controlling other ones of the switching topologies to isolate others of the transmitter and receiver ports from the antenna port;

for a selected one of the receiver or transmitter ports, switching a transistor having a signal path between an associated one of the receiver or transmitter ports and the antenna to an ON state to pass a signal from said associated receiver or transmitter port through said current path of the signal path transistor;

turning off an associated shunt transistor having a drain connected to a gate of the at least one signal path transistor so as to isolate the gate from ground;

for at least one other receiver or transmitter port, switching a transistor having a signal path between an associated one of the receiver or transmitter ports and the antenna to an OFF state; and

turning on an associated shunt transistor having a drain connected to a gate of the at least one other signal path transistor such that the gate is coupled to ground so as to enhance the isolation of the at least one other receiver or transmitter port from the associated receiver or transmitter port.

13. The method of claim 12, and further including the steps of:

arranging at least some of the switching topologies in cascaded stages including a first stage coupled to the antenna port and a last stage coupled to a plurality of the transmitter or receiver ports;

connecting a selected one of the last said transmitter or receiver ports to the antenna ports by switching on the first stage, and switching on a switch associated with said selected one of the last said transmitter or receiver ports wherein the last said switch is a portion of the last stage; and

switching off the remaining switching topologies and other switches in the last stage.

14. The method of claim 13, wherein said step of controlling a selected one of the switching topologies includes the step of switching a plurality of series-connected switching transistors to an ON state.

15. A single-die integrated circuit for switching among a plurality of transmission ports and a plurality of received reports, comprising:

a transmitter switching section having a plurality of transmission ports, said transmitter switching section operable to switch a selected one of the plurality of transmission ports to a transmission node wherein, for each transmission port, the transmission switching section includes a plurality of FETs having current paths coupled in series with each other and operable to couple the transmission port to the transmission node, wherein a last one of the FETs proximate the transmission node has a current path with a first end coupled to the transmission node and a gate;

a first feed-forward capacitor coupled between said first end of said current path and said gate of said last one of the FETs; and

a receiver switching section having a plurality of received ports, said receiver switching section operable to switch a selected one of the plurality of received reports to the transmission node.

16. The integrated circuit of claim 15, further comprising, in each transmitter switching section, a bypass resistor coupled in parallel with the current paths of the plurality of FETs in series.

17. A single-die integrated circuit for switching among a plurality of transmission ports and a plurality of received reports, comprising:

a transmitter switching section having a plurality of transmission ports, said transmitter switching section operable to switch a selected one of the plurality of transmission ports to a transmission node wherein, for each transmission port, the transmission switching section includes a plurality of FETs having current paths coupled in series with each other and operable to couple the transmission port to the transmission node;

a bypass resistor coupled in parallel with the current paths of the plurality of FETs in series; and

a receiver switching section having a plurality of received ports, said receiver switching section operable to switch a selected one of the plurality of received reports to the transmission node.