System and method for on-chip filter tuning

• US 7,515,895 B2
• Filed: 02/04/2005
• Issued: 04/07/2009
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bult, Klaas, Vorenkamp, Pieter, Carr, Frank
• Primary Examiner(s): Vuong; Quochien B
• Application Number:
  US11/050,107
• Publication Number:
  US 20050153677A1
• Time in Patent Office: 1,523 Days
• Field of Search: 455/150.1, 455/193.1, 455/255, 455/258, 455/259, 455/280, 455/307, 455/333, 455/339, 455/340, 333/167, 333/172, 327/552, 327/554, 327/555
• US Class Current: 455/307
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. An apparatus for switching at least one switchable capacitor in a filter, the apparatus comprising:

a regular periodic signal generator that controls timing of switching of each switchable capacitor of a filter, the regular periodic signal generator being operatively coupled to a first input of a filter through a counter;

a control bus operatively coupled between each switchable capacitor and the counter, the counter controlling each switchable capacitor through the control bus; and

a first phase detector operatively coupled between the filter and the counter,

wherein, in a first cycle, more capacitance is added as the counter advances, and

wherein a reset signal to the counter resets the counter for a subsequent cycle.

2. The apparatus according to claim 1, comprising:

means for providing a desired tuning frequency operatively coupled to a second input of the filter

3. The apparatus according to claim 2, comprising:

means for comparing an output of the means for providing a desired tuning frequency to an output of the filter such that at least one switchable capacitor is turned on at the advancement of the counter until the output of the filter is about equal to the output of the means for providing a desired tuning frequency.

4. The apparatus according to claim 3, wherein

at least one switchable capacitor is turned on at the advancement of the counter until it is determined that a phase shift across the filter is zero degrees.

5. The apparatus according to claim 3, comprising:

means for controlling offset, coupled to a third input of the filter, that provides an adjusting signal to manually add or remove at least one switchable capacitor to adjust tuning of the filter if the filter output is not equal to the output of the means for providing a desired tuning frequency.

6. The apparatus according to claim 5, wherein the offset control means comprises an offset control circuit.

7. The apparatus according to claim 1, comprising:

a local oscillator that provides a desired tuning frequency to a second input of the filter.

8. The apparatus according to claim 7, comprising:

a comparator having an input coupled to an output of the first phase detector and having an output coupled to the counter such that when the output of the first phase detector is zero volts, the comparator provides a disabling signal to the counter which prevents any farther switchable capacitors from being switched on.

9. The apparatus according to claim 1, comprising:

means for simultaneously turning off all of the switchable capacitors.

10. The apparatus according to claim 9, wherein the means for simultaneously turning off all of the switchable capacitors comprises a reset circuit that is coupled to the counter, the counter providing an off signal to the filter to eliminate all of the switchable capacitors from the circuit by resetting the counter.

11. The apparatus according to claim 9, wherein the means for simultaneously turning off all of the switchable capacitors is initiated by a controller.

12. The apparatus according to claim 9, wherein the means for simultaneously turning off all of the switchable capacitors is initiated locally.

13. The apparatus according to claim 1, wherein the regular periodic signal generator comprises a reference signal.

14. The apparatus according to claim 1, wherein the regular periodic signal generator comprises a clock.

15. The apparatus according to claim 1, wherein the switchable capacitors have same value and form factor.

16. The apparatus according to claim 1, wherein capacitor values of the switchable capacitors are weighted according to the ratio 1/x, wherein x is an integer.

17. The apparatus according to claim 1, wherein the switchable capacitors are MOS capacitors.

18. The apparatus according to claim 1,

wherein the filter comprises a second input,

wherein the second input of the filter is operatively coupled to an input of the first phase detector, and

wherein an output of the filter is operatively coupled to an input of the first phase detector.

19. The apparatus according to claim 18, comprising:

a comparator operatively coupled between the phase detector and the counter,

wherein an output of the phase detector is operatively coupled to an input of the comparator, and

wherein an output of the comparator is operatively coupled to an input of the counter.

20. The apparatus according to claim 18, comprising:

a second phase detector operatively coupled between the filter and the counter,

wherein the filter filters an input signal that is input to the filter,

wherein the filter outputs a filtered signal,

wherein the first phase detector receives the input signal and the filtered signal, and

wherein the second phase detector receives the input signal and the filtered signal.

21. The apparatus according to claim 20, comprising:

a comparator,

wherein the comparator is operatively coupled between the first phase detector and the counter,

wherein the comparator is operatively coupled between the second phase detector and the counter,

wherein an output of the first phase detector is operatively coupled to the comparator,

wherein an output of the second phase detector is operatively coupled to the comparator, and

wherein an output of the comparator is operatively coupled to an input of the counter.