Recovering from a non-volatile memory failure

• US 7,516,267 B2
• Filed: 11/03/2005
• Issued: 04/07/2009
• Est. Priority Date: 11/03/2005
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Faber, Robert W., Trika, Sanjeev N., Coulson, Richard L.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US11/266,119
• Publication Number:
  US 20070168698A1
• Time in Patent Office: 1,251 Days
• Field of Search: 711/103, 711/113, 711/154, 711/156, 711/161, 711/162, 711/170
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.

Claims

1. A method comprising:

storing a checkpoint of the consumption status of memory locations;

storing a first list of entirely erased memory locations available to be used, said list excluding erased memory locations erased since the storage of said checkpoint; and

storing a second list of entirely erased memory locations not available to be used because they were erased since the storage of said checkpoint, said first and second lists being separate lists.

2. The method of claim 1 comprising:

performing a plurality of write operations to store data in different physical memory locations, each of the physical memory locations being associated with a logical address shared in common among the physical memory locations; and

storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

3. The method of claim 2, further comprising:

storing the logical address in the physical memory locations to indicate which one of the write operations occurred last.

4. The method of claim 2, wherein the physical memory locations are part of a non-volatile memory, the method further comprising:

in response to each of the write operations, updating a logical-to-physical address translation table indicative of a mapping between the logical address and one of the physical memory locations.

5. The method of claim 2, further comprising:

in response to a failure, using the sequence information to reconstruct a logical-to-physical translation table indicative of a mapping between the logical address and one of the physical memory locations.

6. The method of claim 5, further comprising:

in response to a failure, using the sequence information to determine which of the physical memory locations do not store valid data for the logical address.

7. The method of claim 1 including periodically developing a checkpoint indicating the consumption status of memory locations.

8. The method of claim 7 including updating said checkpoint when the number of erased memory locations available to be used falls below a threshold.

9. The method of claim 7 including a response to a failure, reconstructing the consumption status of memory locations using said checkpoint and said list of erased memory locations available to be used.

10. The method of claim 9 including, in the course of updating said checkpoint, transferring locations from said list of erased memory locations not available to be used to said list of memory locations available to be used.

11. The method of claim 10 including maintaining duplicate checkpoints.

12. An apparatus comprising:

a controller;

a volatile memory coupled to said controller;

a non-volatile memory array coupled to said controller; and

a first non-volatile memory location to store a checkpoint of the consumption status of memory locations and a list of erased memory locations available to be used, said list excluding erased memory locations erased since the storage of said checkpoint, and a second list of entirely erased memory locations not available to be used because they were erased since the storage of said checkpoint, said first and second lists being separate lists.

13. The apparatus of claim 12, said controller, in response to failure, to use sequence information to reconstruct a logical-to-physical translation table indicative of the mapping between a logical address and a physical memory location in said non-volatile memory array.

14. The apparatus of claim 13, said controller, in response to a failure, to use the sequence information to determine which of the physical memory locations do not store valid data for the logical address.

15. The apparatus of claim 12, said controller to periodically develop a checkpoint indicating the consumption status of memory locations in said non-volatile memory array.

16. The apparatus of claim 15, said controller to update said checkpoint when the number of erased memory locations available to be used falls below a threshold.

17. The apparatus of claim 15, said controller, in response to a failure, to reconstruct the consumption status of memory locations using said checkpoint and said list of erased memory locations available to be used.

18. The apparatus of claim 17, said controller, in the course of updating said checkpoint, to transfer locations from a list of erased memory locations not available to be used to said list of erased memory locations available to be used.

19. The apparatus of claim 18, said controller to maintain duplicate checkpoints in said non-volatile memory array.

20. The apparatus of claim 19 including a storage to store an indicator to indicate a valid checkpoint of said duplicate checkpoints.

21. A computer readable storage medium storing instructions that, when executed, enable a processor-based system to:

store a checkpoint of the consumption status of memory locations;

store a first list of entirely erased memory locations available to be used, said list excluding erased memory locations erased since the storage of said checkpoint, and

store a second list of entirely erased memory locations not available to be used because they were erased since the storage of said checkpoint, said first and second lists being separate lists.

22. The medium of claim 21 further storing instructions that, when executed, enable the processor-based system, in response to a failure, to use sequence information to reconstruct a logical-to-physical translation table indicative of the mapping between logical address and a physical memory location.

23. The medium of claim 21 further storing instructions that, when executed, enable the processor-based system, in response to a failure, to reconstruct said logical-to-physical translation table using said list of erased memory locations available to be used and not using said list of erased memory locations not available to be used.