Field programmable gate array and microcontroller system-on-a-chip
First Claim
1. An integrated circuit comprising:
- a field programmable gate array (FPGA) core having logic clusters and static random access memory modules, the FPGA core having programmable routing resources;
a system bus configured to convey signals within the integrated circuit;
a FPGA virtual component interface translator coupled to the FPGA core and to the system bus, the FPGA virtual component interface translator configured to translate signals from the FPGA core in a first protocol to the system bus in a second protocol, and from the system bus in the second protocol to the FPGA core in the FPGA core;
a microcontroller coupled to the system bus and to the programmable routing resources;
a microcontroller virtual component interface translator coupled to the microcontroller and the system bus, the microcontroller virtual component interface translator configured to translate signals from the system bus in the second protocol to the microprocessor in a third protocol, and from the microprocessor in the third protocol to the system bus in the second protocol;
programmable routing resources coupled to the FPGA core and to the microcontroller and configured to allow a plurality of programmable connections between the FPGA core and the microcontroller;
a peripheral bus coupled to the system bus through a bridge;
a first dedicated I/O module; and
a first peripheral virtual component interface translator coupled to the first dedicated I/O module through routing resources and to and the peripheral bus, the first peripheral virtual component interface translator configured to translate signals from a fourth protocol in the first dedicated I/O module to the second protocol on the system bus; and
to translate signals from the second protocol on the system bus to the fourth protocol in first dedicated I/O module.
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Abstract
A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
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Citations
10 Claims
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1. An integrated circuit comprising:
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a field programmable gate array (FPGA) core having logic clusters and static random access memory modules, the FPGA core having programmable routing resources; a system bus configured to convey signals within the integrated circuit; a FPGA virtual component interface translator coupled to the FPGA core and to the system bus, the FPGA virtual component interface translator configured to translate signals from the FPGA core in a first protocol to the system bus in a second protocol, and from the system bus in the second protocol to the FPGA core in the FPGA core; a microcontroller coupled to the system bus and to the programmable routing resources; a microcontroller virtual component interface translator coupled to the microcontroller and the system bus, the microcontroller virtual component interface translator configured to translate signals from the system bus in the second protocol to the microprocessor in a third protocol, and from the microprocessor in the third protocol to the system bus in the second protocol; programmable routing resources coupled to the FPGA core and to the microcontroller and configured to allow a plurality of programmable connections between the FPGA core and the microcontroller; a peripheral bus coupled to the system bus through a bridge; a first dedicated I/O module; and a first peripheral virtual component interface translator coupled to the first dedicated I/O module through routing resources and to and the peripheral bus, the first peripheral virtual component interface translator configured to translate signals from a fourth protocol in the first dedicated I/O module to the second protocol on the system bus; and
to translate signals from the second protocol on the system bus to the fourth protocol in first dedicated I/O module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification