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Field programmable gate array and microcontroller system-on-a-chip

  • US 7,516,303 B2
  • Filed: 07/22/2005
  • Issued: 04/07/2009
  • Est. Priority Date: 09/02/2000
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a field programmable gate array (FPGA) core having logic clusters and static random access memory modules, the FPGA core having programmable routing resources;

    a system bus configured to convey signals within the integrated circuit;

    a FPGA virtual component interface translator coupled to the FPGA core and to the system bus, the FPGA virtual component interface translator configured to translate signals from the FPGA core in a first protocol to the system bus in a second protocol, and from the system bus in the second protocol to the FPGA core in the FPGA core;

    a microcontroller coupled to the system bus and to the programmable routing resources;

    a microcontroller virtual component interface translator coupled to the microcontroller and the system bus, the microcontroller virtual component interface translator configured to translate signals from the system bus in the second protocol to the microprocessor in a third protocol, and from the microprocessor in the third protocol to the system bus in the second protocol;

    programmable routing resources coupled to the FPGA core and to the microcontroller and configured to allow a plurality of programmable connections between the FPGA core and the microcontroller;

    a peripheral bus coupled to the system bus through a bridge;

    a first dedicated I/O module; and

    a first peripheral virtual component interface translator coupled to the first dedicated I/O module through routing resources and to and the peripheral bus, the first peripheral virtual component interface translator configured to translate signals from a fourth protocol in the first dedicated I/O module to the second protocol on the system bus; and

    to translate signals from the second protocol on the system bus to the fourth protocol in first dedicated I/O module.

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