System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

• US 7,516,305 B2
• Filed: 12/21/2006
• Issued: 04/07/2009
• Est. Priority Date: 05/01/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Garg, Sanjiv, Deosaran, Trevor, Wang, Johannes
• Primary Examiner(s): Ellis, Richard
• Application Number:
  US11/642,625
• Publication Number:
  US 20070106880A1
• Time in Patent Office: 838 Days
• Field of Search: 712/217, 712/218
• US Class Current: 712/217
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

Claims

1. A superscalar microprocessor for executing instructions having a program order, the microprocessor comprising:

a temporary buffer comprising a plurality of temporary buffer locations configured to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations, each group of temporary buffer locations including a number (N) of the temporary buffer locations, the number N being greater than 1;

tag assignment logic configured to assign tags to instructions, wherein each tag identifies one of the temporary buffer locations, wherein each tag has a first portion that identifies one of the groups of temporary buffer locations and a second portion that identifies one of the temporary buffer locations within the group of temporary buffer locations identified by the first portion of the tag, and

wherein the tag assignment logic is further configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the number of instructions in the first set of instructions is at least 1 and not more than the number N, and wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations;

a plurality of functional units configured to execute instructions from at least the first set of instructions out of the program order, thereby generating result data for each of the instructions in the first set of instructions;

a plurality of data paths configured to transfer result data from the functional units to the temporary buffer, wherein the result data for each instruction in the first set of instructions is transferred to the temporary buffer location identified by the tag assigned to that instruction;

a register array including a plurality of array locations for storing result data for instructions that have been retired;

a retirement control block configured to determine whether execution of all of the instructions in the first set of instructions is complete; and

a superscalar instruction retirement unit configured to concurrently retire all of the instructions in the first set of instructions after execution of all of the instructions in the first set of instructions is complete, wherein retiring at least one of the instructions in the first set of instructions includes transferring the result data for the at least one instruction from the temporary buffer location identified by the tag assigned to the at least one instruction to a selected one of the array locations in the register array.

2. The superscalar microprocessor of claim 1 wherein the respective first portions of the respective tags assigned to the instructions in the first set of instructions are identical to each other and the respective second portions of the respective tags assigned to the instructions in the first set of instructions are different from each other.

3. The superscalar microprocessor of claim 1 wherein:

each of the instructions in the first set of instructions specifies one of the array locations in the register array; and

the instruction retirement unit is further configured to transfer the result data for each of the instructions in the first set of instructions from the temporary buffer location identified by the tag assigned to that instruction to the array location specified by that instruction.

4. The superscalar microprocessor of claim 1 wherein the temporary buffer is configured as a FIFO and wherein each of the groups of temporary buffer locations corresponds to an entry in the FIFO.

5. The superscalar microprocessor of claim 4 wherein the instruction retirement unit is further configured to advance the FIFO by one entry upon retirement of the first set of instructions.

6. The superscalar microprocessor of claim 1 wherein the number N is greater than 2.

7. The superscalar microprocessor of claim 1 wherein the number N is equal to 4.

8. The superscalar microprocessor of claim 1 wherein each of the instructions in the first set of instructions specifies one of the array locations in the register array;

and wherein the respective tags are assigned to each of the instructions in the first set of instructions without regard to the specified array locations.

9. The superscalar microprocessor of claim 1 wherein:

the first set of instructions includes a first instruction and a second instruction, the first instruction preceding the second instruction in the program order;

the second instruction is executed before the first instruction; and

the result data for the second instruction is stored in the temporary buffer location identified by the tag assigned to the second instruction before the result data for the first instruction is stored in the temporary buffer location identified by the tag assigned to the first instruction.

10. The superscalar microprocessor of claim 1 wherein the tag assignment logic is further configured such that after the first set of instructions is retired, the tags assigned to the instructions in the first set of instructions are reassigned to instructions in a second set of instructions, the second set of instructions being subsequent to the first set of instructions in the program order.

11. The superscalar microprocessor of claim 1 wherein the tag assignment logic is configured to concurrently assign a tag to each instruction in a second set of instructions before the instructions in the first set of instructions are retired, wherein the respective tag assigned to each of the instructions in the second set identifies a different one of the temporary buffer locations in a second one of the groups of temporary buffer locations.

12. The superscalar microprocessor of claim 11 wherein each tag has a first portion that identifies one of the groups of temporary buffer locations and a second portion that identifies one of the temporary buffer locations within the group of temporary buffer locations identified by the first portion of the tag.

13. The superscalar microprocessor of claim 12 wherein:

the respective first portions of the respective tags assigned to the instructions in the first set of instructions are identical to each other, and

the respective first portions of the respective tags assigned to the instructions in the second set of instructions are identical to each other and different from the respective first portions of the respective tags assigned to the instructions in the first set of instructions.

14. The superscalar microprocessor of claim 13 wherein:

the respective second portions of the respective tags assigned to the instructions in the first set of instructions are different from each other,

the respective second portions of the respective tags assigned to the instructions in the second set of instructions are different from each other, and

the respective second portion of each of the respective tags assigned to the instructions in the first set of instructions is identical to the respective second portion of exactly one of the respective tags assigned to the instructions in the second set of instructions.

15. A superscalar microprocessor for executing instructions having a program order, the microprocessor comprising:

a temporary buffer comprising a plurality of temporary buffer locations configured to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations, each group of temporary buffer locations including a number (N) of the temporary buffer locations, the number N being greater than 1, wherein the temporary buffer includes exactly two groups of temporary buffer locations;

tag assignment logic configured to assign tags to instructions, wherein each tag identifies one of the temporary buffer locations,

wherein the tag assignment logic is further configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the number of instructions in the first set of instructions is at least 1 and not more than the number N, and wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations;

a plurality of functional units configured to execute instructions from at least the first set of instructions out of the program order, thereby generating result data for each of the instructions in the first set of instructions;

a plurality of data paths configured to transfer result data from the functional units to the temporary buffer, wherein the result data for each instruction in the first set of instructions is transferred to the temporary buffer location identified by the tag assigned to that instruction;

a register array including a plurality of array locations for storing result data for instructions that have been retired;

a retirement control block configured to determine whether execution of all of the instructions in the first set of instructions is complete; and

a superscalar instruction retirement unit configured to concurrently retire all of the instructions in the first set of instructions after execution of all of the instructions in the first set of instructions is complete, wherein retiring at least one of the instructions in the first set of instructions includes transferring the result data for the at least one instruction from the temporary buffer location identified by the tag assigned to the at least one instruction to a selected one of the array locations in the register array.

16. In a superscalar microprocessor, a method of executing instructions having a program order, the method comprising:

receiving a first set of instructions, the first set of instructions including at least one instruction and not more than a number (N) of instructions, the number N being greater than 1;

concurrently assigning a tag to each instruction in the first set of instructions, wherein the tag assigned to each of the instructions in the first set of instructions identifies one of a plurality of temporary buffer locations in a temporary buffer, the temporary buffer locations being configured to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations, each group of temporary buffer locations including the number N of the temporary buffer locations,

wherein each tag has a first portion that identifies one of the groups of temporary buffer locations and a second portion that identifies one of the temporary buffer locations within the group of temporary buffer locations identified by the first portion of the tag, and

wherein the tags are assigned to the instructions in the first set of instructions such that the first portions of the respective tags assigned to the instructions in the first set of instructions are identical to each other and the second portions of the respective tags assigned to the instructions in the first set of instructions are different from each other, and

wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations;

executing the instructions of the first set of instructions, thereby generating result data for each of the instructions in the first set of instructions, wherein at least one of the instructions in the first set of instructions is executed out of the program order;

storing the result data in the temporary buffer, wherein the result data for each instruction in the first set of instructions is transferred to the temporary buffer location identified by the tag assigned to that instruction;

determining whether execution of all of the instructions in the first set of instructions is complete; and

in response to determining that execution of all of the instructions in the first set of instructions is complete, concurrently retiring all of the instructions in the first set of instructions, wherein retiring at least one of the instructions in the first set of instructions includes transferring the result data for the at least one instruction from the temporary buffer locations identified by the tag assigned to the at least one instruction to a selected one array location in a register array.

17. The method of claim 16 wherein:

each of the instructions in the first set of instructions specifies one of the array locations in the register array; and

concurrently retiring all of the instructions in the first set of instructions includes transferring the result data for each of the instructions in the first set of instructions from the temporary buffer location identified by the tag assigned to that instruction to the array location specified by that instruction.

18. The method of claim 16 wherein the temporary buffer is configured as a FIFO and wherein each of the groups of temporary buffer locations corresponds to an entry in the FIFO, the method further comprising:

upon retiring all of the instructions in the first set of instructions, advancing the FIFO by one entry.

19. The method of claim 16 wherein the number N is greater than 2.

20. The method of claim 16 wherein the number N is equal to 4.

21. The method of claim 16 wherein each of the instructions in the first set of instructions specifies one of the array locations in the register array;

and

wherein the respective tags are assigned to each of the instructions in the first set of instructions without regard to the specified array locations.

22. The method of claim 16 wherein:

the first set of instructions includes a first instruction and a second instruction, the first instruction preceding the second instruction in the program order;

executing the instructions in the first set of instructions includes executing the second instruction before executing the first instruction; and

storing the result data in the temporary buffer includes storing the result data for the second instruction in the temporary buffer location identified by the tag assigned to the second instruction prior to storing the result data for the first instruction in the temporary buffer location identified by the tag assigned to the first instruction.

23. The method of claim 16 further comprising:

after retiring the instructions in the first set of instructions, concurrently reassigning the tags that were assigned to the instructions in the first set of instructions to instructions in a second set of instructions, the second set of instructions being subsequent to the first set of instructions in the program order.

24. The method of claim 16 further comprising:

prior to retiring the instructions in the first set of instructions, concurrently assigning a tag to each instruction in a second set of instructions, wherein the respective tag assigned to each of the instructions in the second set identifies one of the temporary buffer locations in a second one of the groups of temporary buffer locations.

25. The method of claim 24 wherein each tag has a first portion that identifies one of the groups of temporary buffer locations and a second portion that identifies one of the temporary buffer locations within the group of temporary buffer locations identified by the first portion of the tag.

26. The method of claim 25 wherein:

the respective first portions of the respective tags assigned to the instructions in the first set of instructions are identical to each other, and

the respective second portions of the respective tags assigned to the instructions in the second set of instructions are identical to each other and different from the respective first portions of the respective tags assigned to the instructions in the first set of instructions.

27. The method of claim 26 wherein:

the respective second portions of the respective tags assigned to the instructions in the first set of instructions are different from each other,

the respective second portions of the respective tags assigned to the instructions in the second set of instructions are different from each other, and

the respective second portion of each of the respective tags assigned to the instructions in the first set of instructions is identical to the respective second portion of exactly one of the respective tags assigned to the instructions in the second set of instructions.