Processor for performing group floating-point operations

• US 7,516,308 B2
• Filed: 05/13/2003
• Issued: 04/07/2009
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/436,340
• Publication Number:
  US 20040049663A1
• Time in Patent Office: 2,156 Days
• Field of Search: 712/4, 712/5, 712/6, 712/7, 712/13, 712/22, 712/222
• US Class Current: 712/222
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A system and method expands a source operand to a width greater than that of a general purpose register or a data path. Operands are provided substantially larger than the data path width of a processor. The general purpose register specifies a memory address from which several data path widths of data are read. A data path functional unit is augmented with dedicated storage to which the memory operand is copied on initial execution of the instruction. Further instructions specifying the same memory address read the dedicated storage to obtain the operand value, upon verification that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch is combined with register operands in the functional unit, producing a result the size of a general register, so no dedicated storage is required for the result.

Claims

1. A processor comprising:

a virtual memory addressing unit;

a data path;

a register file comprising a plurality of registers coupled to the data path;

an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path;

wherein the group floating-point operations include at least one group square root operation that performs a square root computation on each of the multiple floating-point operands.

2. The processor of claim 1 wherein the group floating-point operations involve operating on at least two of the multiple floating-point operands in parallel.

3. The processor of claim 1 wherein the group floating-point operations involve operating on multiple floating-point operands stored in partitioned fields of more than one of the plurality of registers.

4. The processor of claim 1 wherein the group floating-point operations involve operating on multiple floating-point operands stored in partitioned fields of only one of the plurality of registers.

5. The processor of claim 1 wherein each of the multiple floating-point operands for the at least one group square root operation represents a double-precision floating-point value.

6. The processor of claim 1 wherein each of the multiple floating-point operands for the at least one group square root operation represents a single-precision floating-point value.

7. The processor of claim 1 wherein the catenated results are returned to a register in the plurality of registers.

8. The processor of claim 1 wherein the plurality of registers in the register file are general purpose registers that can be used as operand and result registers for group floating-point operations.

9. The processor of claim 1 wherein floating-point values can be stored in registers in a format conforming to IEEE standard 754.

10. The processor of claim 1 wherein the execution unit is capable of performing group floating-point operations on floating-point data of more than one precision.

11. The processor of claim 1 wherein the execution unit is capable of generating and handling floating-point arithmetic exceptions for group floating-point operations.

12. The processor of claim 1 wherein the execution unit is also capable of executing group integer operations in which multiple integer operands stored in partitioned fields of registers are operated on to produce a catenated result.

13. The processor of claim 12 wherein the group integer operations involve operating on at least two of the multiple integer operands in parallel.

14. The processor of claim 12 wherein the group integer operations involve operating on multiple integer operands stored in partitioned fields of more than one of the plurality of registers.

15. The processor of claim 12 wherein the group integer operations involve operating on multiple integer operands stored in partitioned fields of only one of the plurality of registers.

16. The processor of claim 12 wherein:

the group floating-point operations include group add, group subtract, group compare, group multiply and group divide arithmetic operations that operate on catenated floating-point data; and

the group integer operations include group add, group subtract, group compare and group multiply arithmetic operations that operate on catenated integer data.

17. The processor of claim 12 wherein the execution unit is capable of generating and handling fixed-point arithmetic exceptions for group integer operations.

18. The processor of claim 1 wherein the execution unit is capable of performing group integer operations on integer data of more than one precision.

19. The processor of claim 18 wherein the group integer operations include instructions that perform arithmetic operations on integer data having an elemental width of 8 bits, instructions that perform arithmetic operations on integer data having an elemental width of 16 bits and instructions that perform arithmetic operations on integer data having an elemental width of 32 bits.

20. The processor of claim 1 wherein the execution unit is capable of performing group data handling operations including operations that copy, operations that shift, operations that rearrange and operations that resize catenated integer data stored in a register and return catenated results of the operation.

21. The processor of claim 20 wherein the catenated results of the group data handling operation are returned to a register.

22. The processor of claim 1 wherein the execution unit is capable of performing group data handling operations on integer data having a symbol width of 8 bits, group data handling operations on integer data having a symbol width of 16 bits, and group data handling operations on integer data having a symbol width of 32 bits.

23. The processor of claim 1 wherein the execution unit is capable of performing group data handling operations comprising:

a shift left operation that shifts bits of individual data elements catenated in an operand register to the left and clears empty low order bits of the individual data elements to zero;

a first shift right operation that shifts bits of individual data elements catenated in an operand register to the right and fills empty high order bits of the individual data elements with a value equal to a value stored in a sign bit of the individual data element; and

a second shift right operation that shifts bits of individual data elements catenated in an operand register to the right and clears empty high order bits of the individual data elements to zero.

24. The processor of claim 1 further comprising an external interface operable to receive data from an external source at a rate of at least 2 gigabits/second and communicate the received data over the data path.

25. The processor of claim 1 further comprising:

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path.

26. The processor of claim 1 wherein the execution unit is capable of executing a Galois field operation.

30. The processor of claim 1 wherein the group floating-point operations the execution unit is capable of executing include group floating-point arithmetic operations.

31. The processor of claim 30 wherein, on an instruction-by-instruction basis, the execution unit is capable of executing group-floating arithmetic operations on operands of different elemental widths.

32. The processor of claim 31 wherein an elemental width of the group floating-point arithmetic operations is specified by an opcode associated with the operation.

33. The processor of claim 1 wherein, in response to decoding a single instruction specifying a first operand register containing a plurality of equal-sized floating-point data elements stored in partitioned fields of the first operand register and a destination register, the execution unit is operable to generate an absolute value of each of the plurality of data elements in the first operand register to produce a second plurality of data elements and provide the second plurality of data elements as a catenated result to the destination register.

34. The processor of claim 33 wherein the equal-sized floating-point data elements are 32-bits and the first operand register and the destination register are 128-bit registers.

35. The processor of claim 1 wherein, in response to decoding a single instruction specifying a first operand register containing a plurality of equal-sized floating-point data elements stored in partitioned fields of the first operand register and a destination register, the execution unit is operable to generate a negative of each of the plurality of data elements in the first operand register to produce a second plurality of data elements and provide the second plurality of data elements as a catenated result to the destination register.

36. The processor of claim 35 wherein the equal-sized floating-point data elements are 32-bits and the first operand register and the destination register are 128-bit registers.

27. A processor comprising:

a virtual memory addressing unit;

a data path;

a register file comprising a plurality of registers coupled to the data path;

an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path;

wherein the execution unit is configurable to execute a plurality of instruction streams in parallel from a plurality of threads; and

wherein the processor comprises a register file associated with each thread executing in parallel on the execution unit to support processing of the plurality of threads.

28. The processor of claim 27 wherein the execution unit executes instructions from said plurality of instruction streams in a round-robin manner.

29. The processor of claim 28 wherein the processor ensures only one thread from the plurality of threads can handle an exception at any given time.

37. The processor of claim 27 wherein the group floating-point operations involve operating on at least two of the multiple floating-point operands in parallel.

38. The processor of claim 27 wherein the group floating-point operations involve operating on multiple floating-point operands stored in partitioned fields of more than one of the plurality of registers.

39. The processor of claim 27 wherein the group floating-point operations involve operating on multiple floating-point operands stored in partitioned fields of only one of the plurality of registers.

40. The processor of claim 27 wherein each of the multiple floating-point operands represents a double-precision floating-point value.

41. The processor of claim 27 wherein each of the multiple floating-point operands represents a single-precision floating-point value.

42. The processor of claim 27 wherein the catenated results are returned to a register in the plurality of registers.

43. The processor of claim 27 wherein the plurality of registers in the register file are general purpose registers that can be used as operand and result registers for group floating-point operations.

44. The processor of claim 27 wherein floating-point values can be stored in registers in a format conforming to IEEE standard 754.

45. The processor of claim 27 wherein the execution unit is capable of performing group floating-point operations on floating-point data of more than one precision.

46. The processor of claim 27 wherein the execution unit is capable of generating and handling floating-point arithmetic exceptions for group floating-point operations.

47. The processor of claim 27 wherein the execution unit is also capable of executing group integer operations in which multiple integer operands stored in partitioned fields of registers are operated on to produce a catenated result.

48. The processor of claim 47 wherein the group integer operations involve operating on at least two of the multiple integer operands in parallel.

49. The processor of claim 47 wherein the group integer operations involve operating on multiple integer operands stored in partitioned fields of more than one of the plurality of registers.

50. The processor of claim 47 wherein the group integer operations involve operating on multiple integer operands stored in partitioned fields of only one of the plurality of registers.

51. The processor of claim 47 wherein:

the group floating-point operations include group add, group subtract, group compare, group multiply and group divide arithmetic operations that operate on catenated floating-point data; and

the group integer operations include group add, group subtract, group compare and group multiply arithmetic operations that operate on catenated integer data.

52. The processor of claim 47 wherein the execution unit is capable of generating and handling fixed-point arithmetic exceptions for group integer operations.

53. The processor of claim 27 wherein the execution unit is capable of performing group integer operations on integer data of more than one precision.

54. The processor of claim 53 wherein the group integer operations include instructions that perform arithmetic operations on integer data having an elemental width of 8 bits, instructions that perform arithmetic operations on integer data having an elemental width of 16 bits and instructions that perform arithmetic operations on integer data having an elemental width of 32 bits.

55. The processor of claim 27 wherein the execution unit is capable of performing group data handling operations including operations that copy, operations that shift, operations that rearrange and operations that resize catenated integer data stored in a register and return catenated results of the operation.

56. The processor of claim 55 wherein the catenated results of the group data handling operation are returned to a register.

57. The processor of claim 27 wherein the execution unit is capable of performing group data handling operations on integer data having a symbol width of 8 bits, group data handling operations on integer data having a symbol width of 16 bits, and group data handling operations on integer data having a symbol width of 32 bits.

58. The processor of claim 27 wherein the execution unit is capable of performing group data handling operations comprising:

a shift left operation that shifts bits of individual data elements catenated in an operand register to the left and clears empty low order bits of the individual data elements to zero;

a first shift right operation that shifts bits of individual data elements catenated in an operand register to the right and fills empty high order bits of the individual data elements with a value equal to a value stored in a sign bit of the individual data element; and

a second shift right operation that shifts bits of individual data elements catenated in an operand register to the right and clears empty high order bits of the individual data elements to zero.

59. The processor of claim 27 further comprising an external interface operable to receive data from an external source at a rate of at least 2 gigabits/second and communicate the received data over the data path.

60. The processor of claim 27 further comprising:

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path.

61. The processor of claim 27 wherein the execution unit is capable of executing a Galois field operation.

62. The processor of claim 27 wherein the group floating-point operations the execution unit is capable of executing include group floating-point arithmetic operations.

63. The processor of claim 62 wherein, on an instruction-by-instruction basis, the execution unit is capable of executing group-floating arithmetic operations on operands of different elemental widths.

64. The processor of claim 63 wherein an elemental width of the group floating-point arithmetic operations is specified by an opcode associated with the operation.

65. The processor of claim 27 wherein, in response to decoding a single instruction specifying a first operand register containing a plurality of equal-sized floating-point data elements stored in partitioned fields of the first operand register and a destination register, the execution unit is operable to generate an absolute value of each of the plurality of data elements in the first operand register to produce a second plurality of data elements and provide the second plurality of data elements as a catenated result to the destination register.

66. The processor of claim 65 wherein the equal-sized floating-point data elements are 32-bits and the first operand register and the destination register are 128-bit registers.

67. The processor of claim 27 wherein, in response to decoding a single instruction specifying a first operand register containing a plurality of equal-sized floating-point data elements stored in partitioned fields of the first operand register and a destination register, the execution unit is operable to generate a negative of each of the plurality of data elements in the first operand register to produce a second plurality of data elements and provide the second plurality of data elements as a catenated result to the destination register.

68. The processor of claim 67 wherein the equal-sized floating-point data elements are 32-bits and the first operand register and the destination register are 128-bit registers.