ECC control apparatus
First Claim
1. An ECC (Error Check and Correct) control apparatus to be connected between a host and a memory, comprising:
- a data-path circuit which inputs and outputs data to and from the host, and inputs and outputs data to and from the memory;
an enable interface circuit which receives, from the host, a write-enable signal indicating that data is being written to the memory, and outputs the write-enable signal to the memory;
a detecting circuit which detects a protected-data region and a redundant region of write data input from the host and having a predetermined data length;
a code-generating circuit which generates an error-correction code for correcting errors in data of the protected-data region;
a code-inserting circuit which inserts the error-correction code in the redundant region; and
a counter which counts pulses that constitute the write-enable signal,wherein the data-path circuit outputs the write data to the memory in synchronization with a first clock signal generated from the write-enable signal, andthe enable interface circuit masks the write-enable signal when a number of counted pulses reaches a prescribed number based on data items of the write data.
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Accused Products
Abstract
An ECC control apparatus is to be connected between a host and a memory. The apparatus comprises a first input/output circuit, a detecting circuit, a code-generating circuit, a code-inserting circuit, a second input/output circuit. The first input/output circuit inputs and outputs data to and from the host. The detecting circuit detects a protected-data region and a redundant region of write data input to the first input/output circuit and having a predetermined data length. The code-generating circuit generates an error-correction code for correcting errors in data stored in the protected-data region. The code-inserting circuit inserts the error-correction code in the redundant region. The second input/output circuit inputs and outputs data to and from the memory.
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Citations
22 Claims
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1. An ECC (Error Check and Correct) control apparatus to be connected between a host and a memory, comprising:
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a data-path circuit which inputs and outputs data to and from the host, and inputs and outputs data to and from the memory; an enable interface circuit which receives, from the host, a write-enable signal indicating that data is being written to the memory, and outputs the write-enable signal to the memory; a detecting circuit which detects a protected-data region and a redundant region of write data input from the host and having a predetermined data length; a code-generating circuit which generates an error-correction code for correcting errors in data of the protected-data region; a code-inserting circuit which inserts the error-correction code in the redundant region; and a counter which counts pulses that constitute the write-enable signal, wherein the data-path circuit outputs the write data to the memory in synchronization with a first clock signal generated from the write-enable signal, and the enable interface circuit masks the write-enable signal when a number of counted pulses reaches a prescribed number based on data items of the write data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification