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ECC control apparatus

  • US 7,516,371 B2
  • Filed: 02/27/2004
  • Issued: 04/07/2009
  • Est. Priority Date: 02/28/2003
  • Status: Expired due to Fees
First Claim
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1. An ECC (Error Check and Correct) control apparatus to be connected between a host and a memory, comprising:

  • a data-path circuit which inputs and outputs data to and from the host, and inputs and outputs data to and from the memory;

    an enable interface circuit which receives, from the host, a write-enable signal indicating that data is being written to the memory, and outputs the write-enable signal to the memory;

    a detecting circuit which detects a protected-data region and a redundant region of write data input from the host and having a predetermined data length;

    a code-generating circuit which generates an error-correction code for correcting errors in data of the protected-data region;

    a code-inserting circuit which inserts the error-correction code in the redundant region; and

    a counter which counts pulses that constitute the write-enable signal,wherein the data-path circuit outputs the write data to the memory in synchronization with a first clock signal generated from the write-enable signal, andthe enable interface circuit masks the write-enable signal when a number of counted pulses reaches a prescribed number based on data items of the write data.

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