Method for manufacturing a power bus on a chip

• US 7,516,436 B2
• Filed: 07/11/2006
• Issued: 04/07/2009
• Est. Priority Date: 02/10/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hoang, Hy, Long, Tran, Lin, Chong Ming, Chuang, Tatao
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/483,638
• Publication Number:
  US 20060253826A1
• Time in Patent Office: 1,001 Days
• Field of Search: 716/1, 716/11, 716/12, 716/17
• US Class Current: 716/127
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Claims

1. A method for manufacturing power slits in a power bus located on a chip, comprising:

(a) receiving a computer program product that defines locations for the power slits in the power bus, the computer program product comprising a computer usable medium having computer readable program code embodied in the computer usable medium for causing an application program to execute on an operating system of a computer, the computer readable program code comprising,

a computer readable first program code to locate the power bus in a defined region of the chip,

a computer readable second program code to determine a first number of power slits to be generated in a horizontal direction of the power bus,

a computer readable third program code to determine a second number of power slits to be generated in a vertical direction of the power bus, and

a computer readable fourth program code to define the power slits in the horizontal and vertical directions of the power bus according to the first and second numbers of power slits calculated by the computer readable second and third program codes, respectively; and

(b) forming the power slits in the power bus in accordance with the locations defined by the received computer program product.

2. The method of claim 1, wherein the computer program product received in step (a) further comprises:

a computer readable fifth program code to determine a width for the power bus; and

a computer readable sixth program code to determine a length for the power bus;

wherein the computer readable second program code includes code to divide the width of the power bus by a predetermined maximum width of the power slits plus a predetermined first spacing distance between the power slits to determine the first number of power slits to be generated in the horizontal direction of the power bus; and

wherein the computer readable third program code includes code to divide the length of the power bus by a predetermined minimum length of the power slits plus a predetermined second spacing distance between the power slits in the lengthwise direction to determine the second number of power slits to be generated in the vertical direction of the power bus.

3. The method of claim 2, wherein the computer readable fifth and sixth program codes comprise:

code to assign a first starting-point and a first endpoint corresponding to boundaries of the power bus in the horizontal direction;

code to subtract the first starting-point from the first endpoint resulting in a first absolute value;

code to assign a second starting-point and a second endpoint corresponding to boundaries of the power bus in the vertical direction;

code to subtract the second starting-point and the second endpoint resulting in a second absolute value;

code to compare the first absolute value with the second absolute value to determine which is greater;

code to assign the greater value as the length of the power bus; and

code to assign the lesser value as the width of the power bus.

4. The method of claim 3, wherein the computer program product received in step (a) further comprises:

a computer readable seventh program code to receive parameters indicating coordinate value locations for the chip;

wherein the first and second starting-points and the first and second endpoints are coordinate locations obtained from the coordinate values received by the computer readable seventh program code.

5. The method of claim 2, wherein the computer program product received in step (a) further comprises:

a computer readable seventh program code to compare the width for the power bus determined by the computer readable fifth program code to a minimum standard value and invoking the computer readable first program code if the minimum standard value is greater than the width for the power bus.

6. A method for manufacturing power slits in a power bus located on a chip, comprising:

(a) receiving a computer program product that defines locations for power slits in the power bus, the computer program product comprising a computer usable medium having computer readable program code embodied in the medium for causing an application program to execute on an operating system of a computer, the computer readable program code comprising,

a computer readable first program code to locate a power bus in a defined region of a chip;

a computer readable second program code to determine a first number of power slits to be generated in a horizontal direction of the power bus;

a computer readable third program code to determine a second number of power slits to be generated in a vertical direction of the power bus;

a computer readable fourth program code to define the power slits in the horizontal and vertical directions of the power bus according to the first and second numbers of power slits calculated by the computer readable second and third program codes, respectively; and

a computer readable fifth program code to invoke the computer readable first, second, third and fourth program codes until all power buses in the defined region have power slits; and

(b) forming the power slits in the power bus in accordance with the locations defined by the received computer program product.

7. The method of claim 6, wherein the computer program product received in step (a) further comprises:

a computer readable sixth program code to determine a width for the power bus; and

a computer readable seventh program code to determine a length for the power bus;

wherein the computer readable second program code includes code to divide the width of the power bus by a predetermined maximum width of the power slits plus a predetermined first spacing distance between the power slits to determine the first number of power slits to be generated in the horizontal direction of the power bus; and

wherein the computer readable third program code includes code to divide the length of the power bus by a predetermined minimum length of the power slits plus a predetermined second spacing distance between the power slits in the lengthwise direction to determine the second number of power slits to be generated in the vertical direction of the power bus.

8. The method of claim 6, wherein the computer program product received in step (a) further comprises:

a computer readable sixth program code to identify if any power buses in the defined region overlap to form an orthogonal cross section;

a computer readable seventh program code to remove all power slits in the orthogonal cross section;

a computer readable eighth program code to extend first pointer line(s) from a first power slit(s) of a first power bus to an opposite boundary side of the cross section to connect the first power slits(s) of the first power bus;

a computer readable ninth program code to extend second pointer line(s) from a second power slit(s) of a second power bus to an opposite boundary side of the cross section from the second power slits of the second power bus;

a computer readable tenth program code to intersect, logically, the first pointer line(s) with the second pointer line(s) forming a defined hole indicating where to generate power slits.

9. The method of claim 8, wherein the computer readable tenth program code comprises code to logically AND the first pointer line(s) with the second pointer line(s) to form defined holes indicating where to generate power slits.

10. The method of claim 8, wherein the computer readable sixth program code comprises code to evaluate logically where two buses share coordinate values that intersect.

11. The method of claim 8, wherein the computer readable eighth program code includes code to extend the first pointer lines in a 90°

direction.

12. The method of claim 8, wherein the computer readable eighth program code includes code to extend the first pointer lines in a 180°

direction.

13. The method of claim 8, wherein the computer readable ninth program code includes code to extend the second pointer lines in a 90°

direction.

14. The method of claim 8, wherein the computer readable ninth program code includes code to extend the second pointer lines in a 180°

direction.

15. A method for manufacturing power slits in a power bus located on a chip, comprising:

(a) receiving a computer program product that defines locations for the power slits in the power bus located on the chip, the computer program product comprising a computer usable medium having computer readable program code embodied in the medium for causing an application program to execute on an operating system of a computer, the computer readable program code comprising,

a computer readable first program code to compute a number of power slits to be generated in the power bus; and

a computer readable second program code to define the power slits in the power bus according to the number of power slits computed by the computer readable first program code; and

(b) forming the power slits in the power bus in accordance with the locations defined by the received computer program product.