Method for making an electronic device including a poled superlattice having a net electrical dipole moment

• US 7,517,702 B2
• Filed: 12/21/2006
• Issued: 04/14/2009
• Est. Priority Date: 12/22/2005
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Dukovski, Ilija, Halilov, Samed, Hytha, Marek, Mears, Robert J., Huang, Xiangyang, Yiptong, Jean Augustin Chan Sow Fook, Stephenson, Robert John
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US11/614,513
• Publication Number:
  US 20070161138A1
• Time in Patent Office: 845 Days
• Field of Search: 438/3, 257/E21.208, 257/E21.436, 257/E21.663
• US Class Current: 438/3
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10N 30/074 by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
• CPC Class Codes: H10N 30/852 Composite materials, e.g. having 1-3 or 2-2 type connectivity

Abstract

A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.

Claims

1. A method for making an electronic device comprising:

forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment;

each group of layers of the poled superlattice comprising a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon;

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween; and

coupling at least one electrode to the poled superlattice.

2. The method of claim 1 wherein the poled superlattice generates an electrical potential on the at least one electrode based upon a mechanical stress imparted on the poled superlattice.

3. The method of claim 2 further comprising positioning at least one mass adjacent the poled superlattice to impart the mechanical stress thereto based upon movement of the at least one mass.

4. The method of claim 1 wherein the poled superlattice generates an electrical potential on the at least one electrode based upon thermal energy imparted to the poled superlattice.

5. The method of claim 1 further comprising providing a thermal source for causing the poled superlattice to generate an electrical potential on the at least one electrode based upon thermal energy from the thermal source.

6. The method of claim 5 wherein the thermal source comprises a cathode.

7. The method of claim 6 further comprising positioning at least one anode adjacent the cathode.

8. The method of claim 5 further comprising positioning a semiconductor lens adjacent the poled superlattice on a side thereof opposite the cathode.

9. The method of claim 1 wherein the at least one electrode comprises an input electrode coupled to the poled superlattice for inducing a surface acoustic wave thereon, and an output electrode coupled to the poled superlattice and spaced apart from the first electrode.

10. The method of claim 9 wherein the input and output electrodes comprise interdigitated electrodes.

11. The method of claim 1 wherein the at least one electrode comprises a low voltage electrode and a high voltage electrode coupled to the poled superlattice;

and wherein the poled superlattice transforms voltage levels between the low and high voltages.

12. The method of claim 1 wherein the poled superlattice is mechanically deformable based upon an electrical potential on the at least one electrode.

13. The method of claim 12 further comprising forming a backing layer and a matching layer on respective opposing sides of the poled superlattice so that the poled superlattice generates an acoustic signal based upon an electrical potential on the at least one electrode.

14. The method of claim 1 wherein the poled superlattice generates thermal energy based upon an electrical potential on the at least one electrode.

15. The method of claim 1 wherein forming the poled superlattice comprises exposing the superlattice to an electrical field to impart the net electrical dipole moment therein.

16. The method of claim 1 wherein each base semiconductor portion comprises silicon.

17. The method of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

18. The method of claim 1 wherein each non-semiconductor monolayer comprises oxygen.

19. The method of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

20. A method for making an electronic device comprising:

forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment;

each group of layers of the poled superlattice comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer thereon;

the at least one oxygen monolayer being constrained within a crystal lattice of adjacent base semiconductor portions, and at least some silicon atoms from opposing base semiconductor portions being chemically bound together through the at least one oxygen monolayer therebetween; and

coupling at least one electrode to the poled superlattice.

21. The method of claim 20 wherein the poled superlattice generates an electrical potential on the at least one electrode based upon a mechanical stress imparted on the poled superlattice.

22. The method of claim 20 wherein the poled superlattice generates an electrical potential on the at least one electrode based upon thermal energy imparted to the poled superlattice.

23. The method of claim 20 further comprising providing a thermal source for causing the poled superlattice to generate an electrical potential on the at least one electrode based upon thermal energy from the thermal source.

24. The method of claim 20 wherein the at least one electrode comprises an input electrode coupled to the poled superlattice for inducing a surface acoustic wave thereon, and an output electrode coupled to the poled superlattice and spaced apart from the first electrode.

25. The method of claim 20 wherein the at least one electrode comprises a low voltage electrode and a high voltage electrode coupled to the poled superlattice;

and wherein the poled superlattice transforms voltage levels between the low and high voltages.

26. The method of claim 20 wherein the poled superlattice is mechanically deformable based upon an electrical potential on the at least one electrode.

27. The method of claim 20 wherein the poled superlattice generates thermal energy based upon an electrical potential on the at least one electrode.