P-channel MOS transistor and fabrication process thereof

• US 7,518,188 B2
• Filed: 07/14/2005
• Issued: 04/14/2009
• Est. Priority Date: 03/09/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Shimamune, Yosuke, Hatada, Akiyoshi, Katakami, Akira, Tamura, Naoyoshi, Shima, Masashi
• Primary Examiner(s): Lee; Eugene
• Application Number:
  US11/180,791
• Publication Number:
  US 20060202280A1
• Time in Patent Office: 1,370 Days
• Field of Search: 257/616, 257/19, 257/E33.009, 257/347, 257/33.009
• US Class Current: 257/347
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.

Claims

1. A p-channel MOS transistor, comprising:

a monocrystalline silicon substrate;

a gate electrode formed on said monocrystalline silicon substrate in correspondence to a channel region therein via a gate insulation film, said gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof; and

monocrystalline source and drain regions of p-type formed in said monocrystalline substrate at respective outer sides of said sidewall insulation films,

each of said source and drain regions enclosing a polycrystal region of p-type SiGe mixed crystal, said polycrystal region of SiGe mixed crystal accumulating therein a compressive stress,

wherein said polycrystal regions of p-type SiGe mixed crystal in said source and drain regions apply a compressive stress to said channel region,

said polycrystal regions being formed at respective outer sides of said sidewall insulation films,

each of said source and drain regions enclosing said polycrystal region of p-type SiGe mixed crystal being monocrystalline.

2. The p-channel MOS transistor as claimed in claim 1, wherein said polycrystal region comprises polysilicon containing an impurity element having an atomic radius larger than an atomic radius of Si.

3. The p-channel MOS transistor as claimed in claim 1, wherein said polycrystal region comprises polysilicon containing an impurity element in the form of a cluster of atoms constituting said impurity element.

4. The p-channel MOS transistor as claimed in claim 1, wherein said polycrystal region comprises a SiGe polycrystal.

5. The p-channel MOS transistor as claimed in claim 1, wherein said SiGe polycrystal region contains Ge with a concentration near a solubility limit of Ge in a Si crystal.

6. The p-channel MOS transistor as claimed in claim 1, wherein said SiGe polycrystal region contains Ge with a concentration exceeding a solubility limit of Ge in a Si crystal.

7. The p-channel MOS transistor as claimed in claim 2, wherein said polycrystal region contains said impurity element with a concentration near a solubility limit of said impurity element in a Si crystal.

8. The p-channel MOS transistor as claimed in claim 2, wherein said polycrystal region contains said impurity element with a concentration exceeding a solubility limit of said impurity element in a Si crystal.

9. The p-channel MOS transistor as claimed in claim 2, wherein said impurity element comprises any of In and Ge.