Power circuit package and fabrication method

• US 7,518,236 B2
• Filed: 10/26/2005
• Issued: 04/14/2009
• Est. Priority Date: 10/26/2005
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Beaupre, Richard Alfred, Delgado, Eladio Clemente
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US11/259,992
• Publication Number:
  US 20070090464A1
• Time in Patent Office: 1,266 Days
• Field of Search: 257/678, 257/685, 257/686, 257/723, 257/724, 257/726, 257/E25.031, 257/E25.032, 257/E23.042, 438/6, 438/28, 438/66, 438/67, 438/107, 438/109, 438/406, 438455-459, 438FOR 211-FOR 220, 438FOR 365-FOR 368
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/15747 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/145 Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
• CPC Class Codes: H05K 1/147 : at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit H05K1/148 takes precedence

Abstract

A power circuit package includes a base including a substrate, a plurality of interconnect circuit layers over the substrate with each including a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the substrate electrical interconnects; and a power semiconductor module including power semiconductor devices each including device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure including a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections.

Claims

1. A power circuit package comprising:

a base comprising a substrate, a plurality of interconnect circuit layers over the substrate with each comprising a substrate insulating layer patterned with substrate electrical interconnects, and via connections, extending from a top surface of the substrate to at least one of the substrate electrical interconnects;

a power semiconductor module comprising power semiconductor devices each comprising device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure comprising a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections; and

surface mount components coupled to selected substrate electrical interconnects or via connections.

2. The power circuit package of claim 1 wherein the surface mount components comprise at least one component selected from the group consisting of passive surface components and active surface components.

3. The power circuit package of claim 1 wherein the surface mount components comprise at least one passive circuit component from the group consisting of resistors, capacitors, and inductors.

4. The power circuit package of claim 1 wherein the surface mount components comprise at least one active circuit component from the group consisting of gate drive circuits, current sensors, voltage sensors, thermal sensors, processing electronics, optoelectronics, and conditioning electronics.

5. The power circuit package of claim 1 wherein at least some of the via connections are configured for thermal and electrical coupling.

6. The power circuit package of claim 1 further comprising at least two types of solder for coupling of the power semiconductor module and the surface mount components, one type of solder for coupling the power semiconductor module having a higher reflow temperature than another type of solder for coupling at least one surface mount component.

7. The power circuit package of claim 1 further comprising solder configured for coupling of the power semiconductor module.

8. The power circuit package of claim 1 further comprising potting material at least partially surrounding the power semiconductor module.

9. The power circuit package of claim 8 further comprising a frame coupled to the top surface of the substrate and supporting the potting material, wherein the potting material additionally surrounds at least some of the surface mount components.

10. The power circuit package of claim 9 further comprising output connectors coupled to selected electrical interconnects or via connections and partially surrounded by the potting material so as to be accessible for external coupling.

11. A power circuit package comprising:

a base comprising a substrate, a plurality of interconnect circuit layers over the substrate with each comprising a substrate insulating layer patterned with substrate electrical interconnects, and via connections,

extending from a top surface of the substrate to at least one of the substrate electrical interconnects;

a power semiconductor module comprising power semiconductor devices each comprising device cads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure comprising a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections; and

a surface mount component coupled on a top surface of the membrane structure.

12. A power circuit package comprising:

a base comprising a substrate, a plurality of interconnect circuit layers over the substrate with each comprising a substrate insulating layer patterned with substrate electrical interconnects, and via connections, extending from a top surface of the substrate to at least one of the substrate electrical interconnects;

a power semiconductor module comprising power semiconductor devices each comprising device cads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure comprising a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections; and

a heat exchanger and a thermal interface material coupling the heat exchanger and a top surface of the membrane structure.

13. A power circuit package comprising:

a base comprising a substrate, a plurality of interconnect circuit layers over the substrate with each comprising a substrate insulating layer patterned with substrate electrical interconnects, and via connections, extending from a top surface of the substrate to at least one of the substrate electrical interconnects;

a power semiconductor module comprising power semiconductor devices each comprising device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure comprising a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections,

wherein the substrate comprises a metal insulated substrate.

14. The power circuit package of claim 13 wherein the substrate further comprises cooling channels embedded therein.

15. A method for fabricating a power circuit package comprising:

providing a base comprising a substrate, a plurality of interconnect circuit layers over the substrate with each comprising a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the electrical interconnects;

providing a power semiconductor module comprising power semiconductor devices each comprising device pads on a top surface and backside contacts on a bottom surface, the power semiconductor devices being coupled to a membrane structure, the membrane structure comprising a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads;

mounting the power semiconductor module to selected electrical interconnects or via connections of the base.

16. The method of claim 15, further comprising providing surface mount components, and mounting the surface mount components to selected electrical interconnects or via connections of the base.

17. The method of claim 16 further comprising applying potting material at least partially surrounding the power semiconductor module.

18. The method of claim 17 wherein applying the potting material comprises coupling a frame to the top surface of the substrate and supplying the potting material in the frame.

19. The method of claim 16 wherein the surface mount components comprise at least one component selected from the group consisting of passive surface components and active surface components.

20. The method of claim 16 wherein mounting the power semiconductor module and the surface mount components comprises simultaneously soldering the power semiconductor module and the surface mount components.

21. The method of claim 16 wherein mounting the power semiconductor module and the surface mount components comprises soldering the power semiconductor module and then soldering the surface mount components.