Stacked electronics for sensors

• US 7,518,251 B2
• Filed: 12/03/2004
• Issued: 04/14/2009
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Burdick, William Edward Jr., Fisher, Rayette Ann, Rose, James Wilson
• Primary Examiner(s): Chu; Chris C.
• Application Number:
  US11/003,602
• Publication Number:
  US 20060118939A1
• Time in Patent Office: 1,593 Days
• Field of Search: 257684-690, 257/E25.006, 257/E25.013, 257/E21.597, 257/E23.004, 257/E23.011, 257/773, 257/785, 257/780, 257/786, 257/781, 438455-457, 438/109
• US Class Current: 257/785
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81913 Plasma cleaning
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A stacked electronics module comprises a first layer including a first substrate having a front side and a backside, a first electrical interconnect layer disposed on the first substrate and a first electronic device disposed on the front side of the first substrate. In addition, the stacked electronics module comprises a second layer including a second substrate having a front side and a backside, a second electrical interconnect layer disposed on the second substrate and a second electronic device disposed on the front side of the second substrate.

Claims

1. A stacked electronics module comprising:

a first layer comprising a first substrate having a front side and a backside;

a first electrical interconnect layer disposed on the first substrate;

a first electronic device disposed on the front side of the first substrate;

a first plurality of metal pads disposed on the backside of the first substrate;

a second plurality of metal pads disposed on the first plurality of metal pads;

a second layer comprising a second substrate having a front side and a backside;

a second electrical interconnect layer disposed on the second substrate; and

a second electronic device disposed on the front side of the second substrate; and

a plurality of trenches formed in the front side of the second substrate, wherein each of the plurality of trenches is configured to matably receive a respective one of the plurality of metal pads to form an interlocking structure to mechanically align the first layer and the second layer in the x-y direction.

2. The stacked electronics module of claim 1, wherein the first substrate comprises a semiconductor material.

3. The stacked electronics module of claim 1, wherein the second substrate comprises a semiconductor material.

4. The stacked electronics module of claim 1, further comprising a plurality of layers of electronic devices configured for processing a plurality of input signals.

5. The stacked electronics module of claim 4, wherein the electronic device comprises one of a pulser, a beam former, a signal processor, a high-voltage analog circuit, a micro-machined electromechanical system, a sensor, and a switching circuit.

6. The stacked electronics module of claim 1, further comprising a plurality of metal pads disposed on the backside of the second layer, wherein each of the plurality of metal pads disposed on the backside of the first layer is configured to selectively couple with a respective one of the plurality of metal pads disposed on the backside of the second layer.

7. The stacked electronics module of claim 6, further comprising material containing conductive particles disposed on the plurality of metal pads disposed on the backside of the first substrate.

8. The stacked electronics module of claim 1, further comprising material containing conductive particles disposed in the plurality of trenches formed in the front side of the second substrate.

9. The stacked electronics module of claim 1, wherein the plurality of metal pads and the plurality of trenches are electrically conductive.

10. The stacked electronics module of claim 1, further comprising a plurality protrusions disposed on the backside of the first substrate.

11. The stacked electronics module of claim 10, wherein the plurality of trenches formed in the front side of the second layer is aligned to mate with the plurality of protrusions disposed on the backside of the first layer.

12. The stacked electronics module of claim 11, wherein the plurality of trenches is aligned with the plurality of protrusions via dynamic aligning.

13. The stacked electronics module of claim 11, wherein the first layer is coupled to the second layer via fusion bonding.

14. The stacked electronics module of claim 11, further comprising filler material disposed within gaps between the plurality of protrusions and the plurality of trenches.