Barrel shifter implemented on a configurable integrated circuit
First Claim
Patent Images
1. A barrel shifter implemented on an integrated circuit (IC), said barrel shifter comprising:
- a) a first plurality of configurable tiles comprising configurable circuits;
b) a second plurality of configurable tiles comprising configurable circuits; and
c) a first set of non-neighboring offset connections (NNOCs) connecting at least two tiles of said first plurality of configurable tiles to at least two tiles of said second plurality of configurable tiles, wherein said first set of NNOCs is for shifting data words by a particular number of bits, and wherein NNOCs directly connect pairs of tiles that are not aligned with each other and do not neighbor each other, wherein the first set of NNOCs are topologically parallel to each other.
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Abstract
Some embodiments provide a barrel shifter on a configurable integrated circuit (IC). The barrel shifter has a first set of tiles and a second set of tiles with configurable circuits. The barrel shifter also has a first set of non-neighboring offset connections (NNOCs) connecting at least one of the tiles in the first set to at least one of the tiles in the second set.
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Citations
40 Claims
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1. A barrel shifter implemented on an integrated circuit (IC), said barrel shifter comprising:
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a) a first plurality of configurable tiles comprising configurable circuits; b) a second plurality of configurable tiles comprising configurable circuits; and c) a first set of non-neighboring offset connections (NNOCs) connecting at least two tiles of said first plurality of configurable tiles to at least two tiles of said second plurality of configurable tiles, wherein said first set of NNOCs is for shifting data words by a particular number of bits, and wherein NNOCs directly connect pairs of tiles that are not aligned with each other and do not neighbor each other, wherein the first set of NNOCs are topologically parallel to each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 22, 39)
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10. An integrated circuit (IC) for implementing a barrel shifter, said IC comprising:
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a) a first plurality of configurable tiles; b) a second plurality of configurable tiles comprising a first set of interconnect circuits; c) a third plurality of configurable tiles; d) a first set of connections connecting the first plurality of configurable tiles to the second plurality of configurable tiles, comprising a first set of non-neighboring offset connections (NNOCs) connecting at least two tiles of said first plurality of configurable tiles to interconnect circuits of at least two tiles of said second plurality of configurable tiles, wherein said first set of NNOCs is for shifting data words by a first number of bits while passing said data words between said first plurality of configurable tiles and said interconnect circuits of said at least two tiles of said second plurality of configurable tiles; and e) a second set of connections, connecting the second plurality of configurable tiles to the third plurality of configurable tiles, comprising a second set of NNOCs connecting at least two tiles of said second plurality of configurable tiles to at least two tiles of said third plurality of configurable tiles, wherein said second set of NNOCs is for shifting data words by a second number of bits while passing said data words between said second plurality of configurable tiles and said third plurality of configurable tiles, wherein NNOCs directly connect pairs of tiles that are not aligned with each other and do not neighbor each other, and wherein the first set of connections is for shifting said data words by a number of bits between zero and (N−
1) inclusive, wherein N is an integer, and wherein the second set of connections is for shifting said data words by N times M bits, wherein M is an integer or zero. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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23. A method of barrel shifting data on an integrated circuit (IC) comprising a plurality of configurable tiles comprising a first plurality of configurable tiles and a second plurality of configurable tiles, said first plurality of configurable tiles comprising a plurality of configurable circuits, said method comprising:
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a) receiving data at one set of inputs of a plurality of sets of inputs, wherein said one set of inputs comprises one input on each tile of said first plurality of configurable tiles, and wherein said one set of inputs is connected to a set of outputs of said second plurality of configurable tiles by a first set of topologically parallel non-neighboring offset connections (NNOCs), wherein NNOCs directly connect pairs of configurable tiles that are not aligned with each other and do not neighbor each other; and b) ignoring data at multiple other sets of inputs of said plurality of sets of inputs wherein each set of inputs of said multiple other sets of inputs comprises one input on each tile, wherein receiving data at said first set of inputs and ignoring data on said other sets of inputs facilitates a shift of a particular number of bits. - View Dependent Claims (24, 25, 26, 27)
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28. An integrated circuit (IC) comprising:
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a) a first plurality of tiles comprising outputs; b) a second plurality of configurable tiles, each configurable tile of said second plurality of configurable tiles comprising at least one interconnect circuit; c) a bus passing through said first and second pluralities of configurable tiles wherein, between said first and second pluralities of configurable tiles, said bus comprises; i) a first plurality of connections for passing data words from said outputs of said first plurality of tiles to said second plurality of configurable tiles without shifting said data words, and ii) a second plurality of connections for shifting data words by a first number of bits while passing said data words from said first plurality of tiles to said second plurality of configurable tiles, wherein each connection of said second plurality of connections is a non-neighboring offset connection, wherein NNOCs directly connect pairs of tiles that are not aligned with each other and do not neighbor each other; and d) at least one circuit for determining whether to pass the data words in the bus to the first plurality of connections or the second plurality of connections. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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35. An IC comprising:
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a) a first plurality of tiles each tile comprising an output; b) a second plurality of configurable tiles each comprising a plurality of selectable inputs; and c) a plurality of direct connections connecting said outputs to said selectable inputs, wherein said plurality of direct connections comprise non-neighboring offset connections (NNOCs) wherein NNOCs directly connect pairs of tiles that are not aligned with each other and do not neighbor each other; wherein each of a plurality of said outputs is connected to selectable inputs of multiple tiles of said second plurality of configurable tiles by multiple direct connections, wherein at least one of said multiple direct connections is an NNOC, and wherein, when said IC is configured to shift a data word, selectable inputs connected to NNOCs are selected to accept data, wherein at least some NNOCs shifting the data word by a particular number of bits are topologically parallel to each other. - View Dependent Claims (36, 37, 38)
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40. An integrated circuit (IC) for implementing a barrel shifter, said IC comprising:
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a) a first, second, and third plurality of configurable tiles, the second plurality of configurable tiles comprising a first set of interconnect circuits; b) a first set of non-neighboring offset connections (NNOCs) connecting at least two tiles of said first plurality of configurable tiles to interconnect circuits of at least two tiles of said second plurality of configurable tiles, wherein said first set of NNOCs is for shifting data words by a first number of bits while passing said data words between said first plurality of configurable tiles and said interconnect circuits of said at least two tiles of said second plurality of configurable tiles; c) a second set of NNOCs connecting at least two tiles of said second plurality of configurable tiles to at least two tiles of said third plurality of configurable tiles, wherein said second set of NNOCs is for shifting data words by a second number of bits while passing said data words between said second plurality of configurable tiles and said third plurality of configurable tiles, wherein NNOCs directly connect pairs of tiles that are not aligned with each other and do not neighbor each other, wherein connections connecting the first plurality of configurable tiles to the second plurality of configurable tiles are for shifting said data words by any specified numbers of bits within a small range of numbers of bits, and wherein connections connecting the second plurality of configurable tiles to the third plurality of configurable tiles are for shifting said data words by any specified multiple of a preset number of bits within a larger range of numbers of bits.
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Specification