Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs

• US 7,518,402 B2
• Filed: 07/09/2007
• Issued: 04/14/2009
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Hutchings, Brad, Redgrave, Jason, Huang, Randy Renfu, Teig, Steven
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US11/775,218
• Publication Number:
  US 20080018359A1
• Time in Patent Office: 645 Days
• Field of Search: 326 37- 41, 326/47, 326/101
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

Claims

1. An integrated circuit (IC) comprising:

a) an arrangement of tiles comprising a plurality of configurable tiles and a plurality of sides that define a boundary of the arrangement, wherein a first set of tiles among said plurality of configurable tiles each comprise;

i) a configurable logic circuit, and

ii) a plurality of input-select circuits; and

b) a set of direct connections connecting said plurality of input-select circuits of a first tile to a set of outputs of a second set of tiles,

wherein the second set of tiles is located in asymmetrical positions with respect to said first configurable tile, wherein the second set of tiles is located in asymmetrical positions with respect to the first particular tile because;

i) at least one direct connection connects the first particular tile to a second particular tile in the second set, the second particular tile offset from the first particular tile in the arrangement,

ii) the arrangement includes a symmetrical set of tiles, wherein each tile of said symmetrical set of tiles has a positional relationship with the first particular tile that is symmetrical to a positional relationship that the second particular tile has with respect to the first particular tile, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the first particular tile, and

iii) no direct connection connects the first particular tile with any of the symmetrical set of tiles.

2. The IC of claim 1, wherein each of a plurality of configurable logic circuits has a set of input-select circuits associated only with that logic circuit.

3. The IC of claim 2, wherein an input-select circuit is associated with a particular configurable logic circuit when at least one output of said input-select circuit connects to the particular configurable logic circuit.

4. The IC of claim 1, wherein each of a plurality of configurable logic circuits is for performing any of a plurality of operations and each particular configurable logic circuit is configurable by a set of configuration data that specifies at least one operation from said plurality of operations that the particular configurable circuit will perform.

5. The IC of claim 1 further comprising a plurality of configurable tiles that do not have configurable logic circuits.

6. The IC of claim 1, wherein the set of configurable logic circuits in each of a third set of tiles has a set of outputs that are supplied to a set of asymmetric locations in the IC.

7. The IC of claim 1, wherein at least some of said plurality of configurable tiles comprise configurable interconnect circuits for connecting said tiles to other tiles.

8. The IC of claim 7, wherein a configurable interconnect circuit further connects a plurality of circuits within a particular tile.

9. An integrated circuit (IC) comprising:

a) an arrangement of tiles comprising a plurality of configurable tiles and a plurality of sides that define a boundary of the arrangement, wherein a first set of tiles among said plurality of configurable tiles each comprise;

i) a configurable logic circuit, and

ii) a plurality of input-select circuits; and

b) a set of direct connections connecting the configurable logic circuit of a first tile to a set of inputs of a second set of tiles,

wherein the second set of tiles is located in asymmetrical positions with respect to said first configurable tile, wherein the second set of tiles is located in asymmetrical positions with respect to the first particular tile because;

i) at least one direct connection connects the first particular tile to a second particular tile in the second set, the second particular tile offset from the first particular tile in the arrangement,

ii) the arrangement includes a symmetrical set of tiles, wherein each tile of said symmetrical set of tiles has a positional relationship with the first particular tile that is symmetrical to a positional relationship that the second particular tile has with respect to the first particular tile, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the first particular tile, and

iii) no direct connection connects the first particular tile with any of the symmetrical set of tiles.

10. The IC of claim 9, wherein each of a plurality of configurable logic circuits has a set of input-select circuits associated only with that logic circuit.

11. The IC of claim 10, wherein an input-select circuit is associated with a particular configurable logic circuit when at least one output of said input-select circuit connects to the particular configurable logic circuit.

12. The IC of claim 9, wherein each of a plurality of configurable logic circuits is for performing any of a plurality of operations and each particular configurable logic circuit is configurable by a set of configuration data that specifies at least one operation from said plurality of operations that the particular configurable circuit will perform.

13. The IC of claim 9 further comprising a plurality of configurable tiles that do not have configurable logic circuits.

14. The IC of claim 9, wherein at least some of said plurality of configurable tiles comprise configurable interconnect circuits for connecting said tiles to other tiles.

15. The IC of claim 14, wherein a plurality of interconnect circuits each has a set of outputs that are supplied to a set of asymmetric locations in the IC.

16. An electronic device comprising:

an integrated circuit (IC) comprising;

a) an arrangement of tiles comprising a plurality of configurable tiles and a plurality of sides that define a boundary of the arrangement, wherein a first set of tiles among said plurality of configurable tiles each comprise;

i) a configurable logic circuit, and

ii) a plurality of input-select circuits; and

b) a set of direct connections connecting said plurality of input-select circuits of a first tile to a set of outputs of a second set of tiles,

wherein the second set of tiles is located in asymmetrical positions with respect to said first configurable tile, wherein the second set of tiles is located in asymmetrical positions with respect to the first particular tile because;

i) at least one direct connection connects the first particular tile to a second particular tile in the second set, the second particular tile offset from the first particular tile in the arrangement,

ii) the arrangement includes a symmetrical set of tiles, wherein each tile of said symmetrical set of tiles has a positional relationship with the first particular tile that is symmetrical to a positional relationship that the second particular tile has with respect to the first particular tile, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the first particular tile, and

iii) no direct connection connects the first particular tile with any of the symmetrical set of tiles.

17. The IC of claim 16, wherein each of a plurality of configurable logic circuits has a set of input-select circuits associated only with that logic circuit.

18. The IC of claim 17, wherein an input-select circuit is associated with a particular configurable logic circuit when at least one output of said input-select circuit connects to the particular configurable logic circuit.

19. The IC of claim 16, wherein each of a plurality of configurable logic circuits is for performing any of a plurality of operations and each particular configurable logic circuit is configurable by a set of configuration data that specifies at least one operation from said plurality of operations that the particular configurable circuit will perform.

20. An electronic device comprising:

an integrated circuit (IC) comprising;

a) an arrangement of tiles comprising a plurality of configurable tiles and a plurality of sides that define a boundary of the arrangement, wherein a first set of tiles among said plurality of configurable tiles each comprise;

i) a configurable logic circuit, and

ii) a plurality of input-select circuits; and

b) a set of direct connections connecting the configurable logic circuit of a first tile to a set of inputs of a second set of tiles,

wherein the second set of tiles is located in asymmetrical positions with respect to said first configurable tile, wherein the second set of tiles is located in asymmetrical positions with respect to the first particular tile because;

i) at least one direct connection connects the first particular tile to a second particular tile in the second set, the second particular tile offset from the first particular tile in the arrangement,

ii) the arrangement includes a symmetrical set of tiles, wherein each tile of said symmetrical set of tiles has a positional relationship with the first particular tile that is symmetrical to a positional relationship that the second particular tile has with respect to the first particular tile, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the first particular tile, and

iii) no direct connection connects the first particular tile with any of the symmetrical set of tiles.

21. An integrated circuit (IC) comprising:

a) an arrangement of groups of circuits comprising a plurality of configurable circuits and a plurality of sides that define a boundary of the arrangement, wherein a first set of groups of circuits each comprise;

i) a configurable logic circuit, and

ii) a plurality of input-select circuits; and

b) a set of direct connections connecting said plurality of input-select circuits of a first group of circuits to a set of outputs of a second set of groups of circuits, wherein the second set of groups of circuits is located in asymmetrical positions with respect to said first group of circuits, wherein the second set of groups of circuits is located in asymmetrical positions with respect to the first particular group of circuits because;

i) at least one direct connection connects the first particular group of circuits to a second particular group of circuits offset from the first particular group of circuits in the arrangement,

ii) the arrangement includes a symmetrical set of groups of circuits, wherein each group of circuits of said symmetrical set of groups of circuits has a positional relationship with the first particular group of circuits that is symmetrical to a positional relationship that the second particular group of circuits has with the first particular group of circuits, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the first particular group of circuits, and

iii) no direct connection connects the first particular group of circuits with any of the symmetrical set of groups of circuits.

22. An integrated circuit (IC) comprising:

a) an arrangement of tiles comprising a plurality of configurable tiles and a plurality of sides that define a boundary of the arrangement, wherein a first set of tiles among said plurality of configurable tiles each comprise;

i) a configurable logic circuit, and

ii) a plurality of input-select circuits; and

b) a set of direct connections connecting said plurality of input-select circuits of a first tile to a set of outputs of a second set of tiles,

wherein a second particular tile that is in the second set of tiles is located in a position that is not symmetrical with respect to the position of any other second-set tile relative to the first configurable tile,

wherein the arrangement of tiles includes a third set of tiles that are symmetrical, with respect to at least one of a horizontal axis and a vertical axis through the first particular tile, to the second particular tile.