Liquid crystal display device and fabricating method thereof

• US 7,518,666 B2
• Filed: 06/03/2005
• Issued: 04/14/2009
• Est. Priority Date: 06/05/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Ji No, Kwack, Hee Young, Jung, Tae Yong
• Primary Examiner(s): Nelms; David
• Assistant Examiner(s): Nguyen; Thanh-Nhan P
• Application Number:
  US11/143,657
• Publication Number:
  US 20050270434A1
• Time in Patent Office: 1,411 Days
• Field of Search: 349/38, 349 43- 47
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A TFT substrate having a storage capacitor with an increased capacitance and aperture ratio, and a simplified method of fabricating the same, includes gate and data lines crossing each other to define pixel areas; a gate insulating film between the gate and data lines; TFTs connected to the gate and data lines; a semiconductor pattern defining a channel of the TFTs and overlapped by the data lines; a passivation film covering the data lines and the TFTs; and at least one pixel electrode connected to a TFT and provided within a pixel hole that is arranged within a pixel area. The pixel hole is formed through the passivation film and partially through the gate insulating film. Further, a storage capacitor includes a portion of the pixel electrode that overlaps with an underlying gate line with a portion of the gate insulating film that defines the pixel hole.

Claims

1. A liquid crystal display device, comprising:

a gate line;

a data line crossing the gate line thereby defining pixel area;

a gate insulating film between the gate and data lines;

a thin film transistor connected to the gate and data lines;

a semiconductor layer defining a channel of each thin film transistor;

a passivation film on the data line and on the thin film transistor;

a pixel hole corresponding to a pixel area, wherein the pixel hole passes through the passivation film and at least partially through the gate insulating film; and

a pixel electrode within the pixel hole, wherein a portion of the pixel electrode is on the gate insulating film and overlaps a portion of the gate line to form a storage capacitor,

wherein a thickness of the gate insulating film outside the pixel hole is greater than a thickness of the gate insulating film on the portion of the gate line forming the storage capacitor within the pixel hole.

2. The device of claim 1, wherein the data line overlaps the semiconductor layer.

3. The device of claim 1, wherein the pixel electrode contacts a side surface of a drain electrode of the thin film transistor.

4. The device of claim 3, further comprising a first contact hole through the gate insulating film.

5. The device of claim 4, wherein the first contact hole is aligned within the pixel hole.

6. The device of claim 1, further comprising:

a gate pad, the gate pad including a lower gate pad electrode connected to the gate line, and an upper gate pad electrode connected to the lower gate pad electrode.

7. The device of claim 6, further comprising a second contact hole through the gate insulating film and the passivation film.

8. The device of claim 7, wherein the upper gate pad electrode contacts the lower gate pad electrode via the second contact hole.

9. The device of claim 6, wherein the upper gate pad electrode comprises a transparent conductive material.

10. The device of claim 8, wherein the upper gate pad electrode contacts a side surface of the passivation film.

11. The device of claim 1, further comprising:

a data pad, the data pad including a lower data pad electrode connected to the data line, and an upper data pad electrode connected to the lower data pad electrode.

12. The device of claim 11, further comprising a third contact hole through at least one of the passivation film, the lower data pad electrode, and the semiconductor layer.

13. The device of claim 11, wherein the upper data pad electrode contacts the lower data pad electrode via the third contact hole.

14. The device of claim 11, wherein the upper data pad electrode comprises a transparent conductive material.

15. The device of claim 11, wherein the upper data pad electrode contacts a side surface of the passivation film.

16. The device of claim 1, wherein the pixel electrode comprises a transparent conductive material.

17. The device of claim 1, wherein the pixel electrode contacts a side surface of the passivation film.

18. A method of fabricating a liquid crystal display device, comprising:

forming a gate metal pattern on a substrate, wherein the gate metal pattern includes a gate line and a gate electrode;

forming a gate insulating film on the gate metal pattern;

sequentially forming a semiconductor pattern and a data metal pattern on the gate insulating film, wherein the data metal pattern includes a data line, a source electrode, and a drain electrode;

forming a passivation film on the data metal pattern;

forming a pixel hole through the passivation film and at least partially through the gate insulating film, wherein a portion of the drain electrode is exposed by the pixel hole; and

forming a pixel electrode within the pixel hole, wherein the pixel electrode contacts the exposed portion of the drain electrode, and a portion of the pixel electrode is on the gate insulating film and overlaps a portion of the gate line to form a storage capacitor, and

wherein a thickness of the gate insulating film outside the pixel hole is greater than a thickness of the gate insulating film on the portion of the gate line forming the storage capacitor within the pixel hole.

19. The method of claim 18, further comprising:

forming a first contact hole through the gate insulating film, wherein the first contact hole is aligned within the pixel hole.

20. The method of claim 19, wherein forming the first contact hole comprises:

forming a photo-resist film on the passivation film;

arranging a resist mask over the photo-resist film;

photolithographically patterning the photo-resist film using the resist mask to form a photo-resist pattern; and

etching the gate insulating film using the photo-resist pattern as a mask.

21. The method of claim 20, wherein forming the pixel hole comprises:

removing a first portion of the photo-resist pattern such that a second portion of the photo-resist pattern remains, thereby partially exposing the passivation film; and

etching the partially exposed passivation film.

22. The method of claim 21, wherein the first portion of the photo-resist pattern is thinner than the second portion of the photo-resist pattern.

23. The method of claim 21, wherein etching the partially exposed passivation film comprises:

partially exposing the gate insulating film; and

etching the partially exposed gate insulating film.

24. The method of claim 21, wherein forming the plurality of pixel electrodes comprises:

forming a transparent conductive material on the second portion of the photo-resist pattern and within pixel hole; and

removing the second portion of the photo-resist pattern having the transparent conductive material thereon.

25. The method of claim 20, wherein the resist mask includes a halftone mask.

26. The method of claim 20, wherein the resist mask includes a diffractive exposure mask.

27. The method of claim 20, wherein removing the first portion of the photo-resist pattern includes performing an ashing process after forming the first contact hole.

28. The method of claim 24, wherein the removing the second portion of the photo-resist pattern includes performing a lift-off process.

29. The method of claim 19, further comprising:

forming a lower gate pad electrode simultaneously with the forming of the gate line and gate electrode, wherein the lower gate pad electrode is connected to the gate line;

forming a second contact hole within the gate insulating and passivation films simultaneously with the forming of the first contact hole, wherein at least a portion of the lower gate pad electrode is exposed within the second contact hole; and

forming an upper gate pad electrode within the second contact hole, wherein the upper gate pad electrode contacts the lower gate pad electrode.

30. The method of claim 19, further comprising:

forming a lower data pad electrode using the second mask simultaneously with the formation of the data line and the source and drain electrodes, wherein the lower data pad electrode is connected to a data line and the semiconductor pattern;

forming a third contact hole within at least one of the passivation film, the lower data pad electrode, and the semiconductor pattern simultaneously with the forming of the first contact hole, wherein at least a portion of at least one of the lower data pad electrode and the semiconductor pattern is exposed within the third contact hole; and

forming an upper data pad electrode within the third contact hole, wherein the upper data pad electrode contacts the lower data pad electrode.

31. The method of claim 30, wherein the upper data pad electrode contacts a side surface of the lower data pad electrode.