Interposer containing bypass capacitors for reducing voltage noise in an IC device

• US 7,518,881 B2
• Filed: 07/20/2007
• Issued: 04/14/2009
• Est. Priority Date: 06/17/2004
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornelius, William P.
• Primary Examiner(s): Dinh; Tuan T
• Application Number:
  US11/781,116
• Publication Number:
  US 20070291448A1
• Time in Patent Office: 634 Days
• Field of Search: 361760-765, 361/795, 361/803, 257685-686
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Claims

1. A computer system including a mechanism for reducing voltage noise for a processor chip, comprising:

one or more processors located on the processor chip;

a memory that stores instructions and data for the one or more processors;

an interposer sandwiched between the processor chip and a circuit board;

wherein the interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip; and

a plurality of bypass capacitors, each including a set of internal planes, integrated into the interposer and coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the processor chip, wherein the internal planes of the bypass capacitors extend downward from the top surface of the interposer in a direction that is normal to the top surface of the interposer;

wherein the plurality of bypass capacitors are electrically connected to power and ground conductors on the top surface of the interposer, so that step currents caused by the processor chip which is coupled to the top surface of the interposer enter and leave the plurality of bypass capacitors through the top surface of the interposer.

2. The computer system of claim 1,

wherein distal ends of the internal planes of the plurality of bypass capacitors, which are located farthest from the top the interposer, are electrically connected to power and ground conductors on the bottom surface of the interposer;

whereby the internal planes of the plurality of bypass capacitors function as power and ground leads that electrically couple the power and ground connections from the circuit board with power and ground connections on the processor chip.

3. The computer system of claim 1, wherein the bottom surface of the interposer has the same electrical connections in the same locations as the processor chip, whereby the interposer can be attached to a circuit board which is configured to be connected directly the processor chip without having to reconfigure the circuit board to accommodate the interposer.

4. The computer system of claim 1,

wherein the interposer is sandwiched between the circuit board and a package for the processor chip;

wherein the processor chip is bonded to the top surface of the package; and

wherein the bottom surface of the package is bonded to the top surface of the interposer.

5. The computer system of claim 1,

wherein the interposer is sandwiched between the processor chip and a package for the processor chip;

wherein the processor chip is bonded to the top surface of the interposer; and

wherein the bottom surface of the interposer is bonded to the top surface of the package.

6. The computer system of claim 1, wherein the interposer contains vias for routing power, ground, and other signals from the top surface of the interposer to the bottom surface of the interposer.