System and method for an asynchronous data buffer having buffer write and read pointers

• US 7,519,788 B2
• Filed: 06/04/2004
• Issued: 04/14/2009
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Farrokh; Hashem
• Application Number:
  US10/861,145
• Publication Number:
  US 20050286506A1
• Time in Patent Office: 1,775 Days
• Field of Search: 711/5, 711/167, 365/233.1
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Claims

1. A memory hub, comprising:

a link interface receiving memory requests for access to memory locations in at least one memory device;

a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;

a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and

a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;

a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;

a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;

a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;

a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and

a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate and provide the write-read pointer offset signal indicative of the comparison to the memory controller.

2. The memory hub of claim 1 wherein the memory controller is further adapted to adjust the timing at which a write memory request immediately following a read memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

3. The memory hub of claim 1 wherein the memory controller is further adapted to adjust the timing at which a read memory request immediately following a write memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

4. The memory hub of claim 1 wherein the read data synchronizing circuit further comprises a data latch coupled to the output terminal of the multiplexer to latch the read data selectively coupled thereto responsive to the core clock signal.

5. The memory hub of claim 1 wherein the read pointer circuit of the read data synchronizing circuit comprises a plurality of flip-flops adapted to output a respective bit of a count value in response to the core clock signal.

6. The memory hub of claim 5 wherein the write pointer circuit of the read data synchronizing circuit comprises:

a first set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series coupled flip-flops shifting a flag through each flip-flop in response to a rising edge of the strobe signal; and

a second set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the second set of series coupled flip-flops shifting a flag through each flip-flop in response to a falling edge of the strobe signal,

the write pointer signal represented by output signals of the flip-flops of the first and second sets of series coupled flip-flops.

7. The memory hub of claim 6 wherein the write-read compare circuit comprises:

a logic circuit having a plurality of input nodes coupled to outputs of each flip-flop of the first and second sets of series coupled flip-flops and further having a plurality of output nodes, the logic circuit adapted to generate flag signals at each of the output nodes indicative of the location of the flag in the first and second sets of series coupled flip-flops;

a first multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the first multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit; and

a second multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the second multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit,

the outputs of the first and second multiplexers providing signals representative the write-read pointer offset signal.

8. The memory hub of claim 7 wherein the logic circuit comprises a plurality of three-input logic OR gates, each logic OR gate having first and second inputs coupled to outputs of two flip-flops of the first set of series coupled flip-flops and further having a third input coupled to an output of a respective flip-flop of the second set of series coupled flip-flops.

9. The memory hub of claim 7 wherein the read data synchronizing circuit further comprises:

a first pair of series coupled flip-flops coupled to the output terminal of the first multiplexer, the first pair of series coupled flip-flops shifting the output of the first multiplexer though the flip-flops in response to the core clock signal; and

a second pair of series coupled flip-flops coupled to the output terminal of the second multiplexer, the second pair of series coupled flip-flops shifting the output of the second multiplexer though the flip-flops in response to the core clock signal.

10. A memory hub, comprising:

a link interface receiving memory requests for access to memory locations in at least one memory device;

a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;

a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and

a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;

a data buffer having a plurality of memory locations at which to store data and a selection signal node, the data buffer coupled to the memory device to store read data at a respective one of the plurality of data locations selected in accordance with a selection signal;

a write pointer circuit coupled to the memory device to receive a data strobe signal and further coupled to the selection signal node of the data buffer to provide a selection signal to sequentially select a data location to which read data from the memory device is written in response to the data strobe signal;

a multiplexer having a plurality of input terminals coupled to a respective one of the plurality of data locations of the data buffer and further having an output terminal to which the input terminals are selectively coupled to couple read data from the data buffer to the output terminal according to a multiplexer selection signal applied to a multiplexer selection node;

a read pointer circuit having a clock node to which the core clock signal is applied and further having an output node coupled to the multiplexer selection node to provide the multiplexer selection signal to sequentially select the input terminals for coupling to the output terminal of the multiplexer responsive to the core clock signal; and

a pointer comparison circuit coupled to the write and read pointer circuits to compare to which one of the data locations read data received from the memory device are currently stored and from which one of the data locations read data are currently coupled to the output terminal of the multiplexer and generate a write-read pointer offset signal indicative of the comparison.

11. The memory hub of claim 10 wherein the memory controller is further adapted to adjust the timing at which a write memory request immediately following a read memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

12. The memory hub of claim 10 wherein the memory controller is further adapted to adjust the timing at which a read memory request immediately following a write memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

13. The memory hub of claim 10 wherein the data synchronizing circuit further comprises a data latch coupled to the output terminal of the multiplexer to latch the read data selectively coupled thereto responsive to the core clock signal.

14. The memory hub of claim 10 wherein the read pointer circuit of the data synchronizing circuit comprises a plurality of flip-flops adapted to output a respective bit of a count value in response to the core clock signal.

15. The memory hub of claim 14 wherein the write pointer circuit of the data synchronizing circuit comprises:

a first set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series coupled flip-flops shifting a flag through each flip-flop in response to a rising edge of the data strobe signal; and

a second set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the second set of series coupled flip-flops shifting a flag through each flip-flop in response to a falling edge of the data strobe signal,

the selection signal represented by output signals of the flip-flops of the first and second sets of series coupled flip-flops.

16. The memory hub of claim 15 wherein the pointer comparison circuit comprises:

a logic circuit having a plurality of input nodes coupled to outputs of each flip-flop of the first and second sets of series coupled flip-flops and further having a plurality of output nodes, the logic circuit adapted to generate flag signals at each of the output nodes indicative of the location of the flag in the first and second sets of series coupled flip-flops;

a first multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the first multiplexer selectively coupling one of the input terminals to the output terminal according to the multiplexer selection signal provided by the read pointer circuit; and

a second multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the second multiplexer selectively coupling one of the input terminals to the output terminal according to the multiplexer selection signal provided by the read pointer circuit,

the outputs of the first and second multiplexers providing signals representative the write-read pointer offset signal.

17. The memory hub of claim 16 wherein the logic circuit comprises a plurality of three-input logic OR gates, each logic OR gate having first and second inputs coupled to outputs of two flip-flops of the first set of series coupled flip-flops and further having a third input coupled to an output of a respective flip-flop of the second set of series coupled flip-flops.

18. The memory hub of claim 16 wherein the data synchronizing circuit further comprises:

a first pair of series coupled flip-flops coupled to the output terminal of the first multiplexer, the first pair of series coupled flip-flops shifting the output of the first multiplexer though the flip-flops in response to the core clock signal; and

a second pair of series coupled flip-flops coupled to the output terminal of the second multiplexer, the second pair of series coupled flip-flops shifting the output of the second multiplexer though the flip-flops in response to the core clock signal.

19. A memory module, comprising:

a plurality of memory devices;

a memory bus coupled to the plurality of memory devices; and

a memory hub coupled to the plurality of memory devices through the memory bus, the memory hub, comprising;

a link interface receiving memory requests for access to memory locations in at least one memory device;

a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;

a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and

a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;

a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;

a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;

a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;

a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and

a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate and provide the write-read pointer offset signal indicative of the comparison to the memory controller.

20. The memory module of claim 19 wherein the memory controller of the memory hub is further adapted to adjust the timing at which a write memory request immediately following a read memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

21. The memory module of claim 19 wherein the memory controller of the memory hub is further adapted to adjust the timing at which a read memory request immediately following a write memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

22. The memory module of claim 19 wherein the read data synchronizing circuit of the memory hub further comprises a data latch coupled to the output terminal of the multiplexer to latch the read data selectively coupled thereto responsive to the core clock signal.

23. The memory module of claim 19 wherein the read pointer circuit of the read data synchronizing circuit comprises a plurality of flip-flops adapted to output a respective bit of a count value in response to the core clock signal.

24. The memory hub of claim 23 wherein the write pointer circuit of the read data synchronizing circuit comprises:

a first set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series coupled flip-flops shifting a flag through each flip-flop in response to a rising edge of the strobe signal; and

a second set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the second set of series coupled flip-flops shifting a flag through each flip-flop in response to a falling edge of the strobe signal,

the write pointer signal represented by output signals of the flip-flops of the first and second sets of series coupled flip-flops.

25. The memory module of claim 24 wherein the write-read compare circuit comprises:

a logic circuit having a plurality of input nodes coupled to outputs of each flip-flop of the first and second sets of series coupled flip-flops and further having a plurality of output nodes, the logic circuit adapted to generate flag signals at each of the output nodes indicative of the location of the flag in the first and second sets of series coupled flip-flops;

a first multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the first multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit; and

a second multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the second multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit,

the outputs of the first and second multiplexers providing signals representative the write-read pointer offset signal.

26. The memory module of claim 25 wherein the logic circuit comprises a plurality of three-input logic OR gates, each logic OR gate having first and second inputs coupled to outputs of two flip-flops of the first set of series coupled flip-flops and further having a third input coupled to an output of a respective flip-flop of the second set of series coupled flip-flops.

27. The memory module of claim 25 wherein the read data synchronizing circuit further comprises:

a first pair of series coupled flip-flops coupled to the output terminal of the first multiplexer, the first pair of series coupled flip-flops shifting the output of the first multiplexer though the flip-flops in response to the core clock signal; and

a second pair of series coupled flip-flops coupled to the output terminal of the second multiplexer, the second pair of series coupled flip-flops shifting the output of the second multiplexer though the flip-flops in response to the core clock signal.

28. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a controller coupled to a system memory port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller;

a memory bus coupled to the system controller for transmitting memory requests and responses thereon; and

a plurality of memory modules coupled to the memory bus, each of the modules having;

a plurality of memory devices; and

a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising;

a link interface receiving memory requests for access to memory locations in at least one memory device;

a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;

a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and

a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;

a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;

a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;

a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;

a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and

a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate and provide the write-read pointer offset signal indicative of the comparison to the memory controller.

29. The processor-based system of claim 28 wherein the memory controller of the memory hub is further adapted to adjust the timing at which a write memory request immediately following a read memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

30. The processor-based system of claim 28 wherein the memory controller of the memory hub is further adapted to adjust the timing at which a read memory request immediately following a write memory request is coupled to the memory device interface responsive to the write-pointer offset signal.

31. The processor-based system of claim 28 wherein the read data synchronizing circuit of the memory hub further comprises a data latch coupled to the output terminal of the multiplexer to latch the read data selectively coupled thereto responsive to the core clock signal.

32. The processor-based system of claim 28 wherein the read pointer circuit of the read data synchronizing circuit comprises a plurality of flip-flops adapted to output a respective bit of a count value in response to the core clock signal.

33. The processor-based system of claim 32 wherein the write pointer circuit of the read data synchronizing circuit comprises:

a first set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series coupled flip-flops shifting a flag through each flip-flop in response to a rising edge of the strobe signal; and

a second set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the second set of series coupled flip-flops shifting a flag through each flip-flop in response to a falling edge of the strobe signal,

the write pointer signal represented by output signals of the flip-flops of the first and second sets of series coupled flip-flops.

34. The processor-based system of claim 33 wherein the write-read compare circuit comprises:

a logic circuit having a plurality of input nodes coupled to outputs of each flip-flop of the first and second sets of series coupled flip-flops and further having a plurality of output nodes, the logic circuit adapted to generate flag signals at each of the output nodes indicative of the location of the flag in the first and second sets of series coupled flip-flops;

a first multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the first multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit; and

a second multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the second multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit,

the outputs of the first and second multiplexers providing signals representative the write-read pointer offset signal.

35. The processor-based system of claim 34 wherein the logic circuit comprises a plurality of three-input logic OR gates, each logic OR gate having first and second inputs coupled to outputs of two flip-flops of the first set of series coupled flip-flops and further having a third input coupled to an output of a respective flip-flop of the second set of series coupled flip-flops.

36. The processor-based system of claim 34 wherein the read data synchronizing circuit further comprises:

a first pair of series coupled flip-flops coupled to the output terminal of the first multiplexer, the first pair of series coupled flip-flops shifting the output of the first multiplexer though the flip-flops in response to the core clock signal; and

a second pair of series coupled flip-flops coupled to the output terminal of the second multiplexer, the second pair of series coupled flip-flops shifting the output of the second multiplexer though the flip-flops in response to the core clock signal.

37. A method of adjusting the timing of retrieving read data from a buffer, the method comprising:

requesting read data from at least one memory device;

sequentially selecting data locations of the buffer at which read data are stored responsive to a strobe signal provided by the memory device, the currently selected data location at which read data is stored identified by a write pointer incremented responsive to the strobe signal;

sequentially selecting data locations of the buffer from which stored read data is retrieved response to a core clock signal, the currently selected data location from which read data is retrieved identified by a read pointer incremented responsive to the core clock signal;

comparing the write pointer and the read pointer to determine a write-read pointer offset indicative of the relative timing between storing the read data to a data location and retrieving the read data from the data location; and

based on the write-read pointer offset, decreasing the time between storing the read data in a data location in the buffer and retrieving read data from the buffer in response to the write-read pointer offset indicative of a data location offset greater than initial number of data locations.

38. The method of claim 37 wherein adjusting the timing of retrieving read data from the buffer relative to the storing of the read data in a data location in the buffer comprises increasing the time between storing the read data in a data location in the buffer and retrieving read data from the buffer in response to the write-read pointer offset indicative of a data location offset less than a initial number of data locations.

39. The method of claim 37 wherein adjusting the timing of retrieving read data from the buffer relative to the storing of the read data in a data location in the buffer comprises adjusting the timing when no memory requests are pending.

40. The method of claim 37 wherein comparing the write pointer and the read pointer to determine a write-read pointer offset comprises comparing the write pointer and the read pointer during a burst memory read operation.

41. The method of claim 37 wherein sequentially selecting data locations of the buffer at which read data are stored responsive to a strobe signal provided by the memory device comprises shifting a first flag bit in response to a rising edge of a strobe signal through a first set of series coupled flip-flops having a last flip-flop coupled to a first flip-flop of the set and shifting a second flag bit in response to a falling edge of the strobe signal through a second set of series coupled flip-flops having a last flip-flop coupled to a first flip-flop of the set.

42. A method of adjusting the relative timing between issuing memory write commands and memory read commands, the method comprising:

storing read data provided by at least one memory device in sequentially selected data locations of a buffer, the data location at which read data are currently stored selected by a write pointer;

retrieving read data stored in the buffer from sequentially selected data locations, the data location from which read data are currently retrieved selected by a read pointer;

generating a write-read pointer offset indicative of a data location offset between the data location selected by the write pointer and the data location selected by the read pointer;

and adjusting the timing between the issuance of a memory write command immediately following a memory read command based on the write-read pointer offset.

43. The method of claim 42 wherein adjusting the timing between the issuance of memory write commands and memory read commands based on the write-read pointer offset comprises adjusting the timing between the issuance of a memory read command immediately following a memory write command based on the write-read pointer offset.

44. The method of claim 42 wherein adjusting the timing between the issuance of memory write commands and memory read commands based on the write-read pointer offset comprises adjusting the timing when no memory requests are pending.

45. The method of claim 42 wherein generating the write-read pointer offset comprises comparing the write pointer and the read pointer during a burst memory read operation and generating the write-read pointer in response to the comparison.

46. The method of claim 42 wherein storing read data provided by at least one memory device in sequentially selected data locations of a buffer comprises shifting a first flag bit in response to a rising edge of a strobe signal through a first set of series coupled flip-flops having a last flip-flop coupled to a first flip-flop of the set and shifting a second flag bit in response to a falling edge of the strobe signal through a second set of series coupled flip-flops having a last flip-flop coupled to a first flip-flop of the set to provide a buffer selection signal for sequentially selecting the data locations.