Method and apparatus for exception handling in a multi-processing environment
First Claim
1. A network element for routing traffic between networks, compnsing:
- a first line card coupled to a first network;
a second line card coupled to a second network different than the first network;
a control card coupled to the first line card and the second line card for routing network traffic between the first and second networks via the first line card and the second line card, the control card includinga plurality of processors including a first processor and a second processor,a memory includinga common exception handling vector address space shared by the plurality of processors, anda plurality of exception handling vector address spaces each associated with each of the plurality of processors,including a first exception and a second exception handling vector address spaces associated with the first and second processors respectively,a memory controller coupled to the memory and the plurality of processors, wherein the first processor is to execute a first operating system, wherein the first operating system is a real-time operating system to handle routing network traffic, andwherein the second processor is to execute a second operating system and to execute one or more instructions in the common exception handling vector address space upon receipt of an exception, wherein the second operating system is a non-real-time operating system to handle at least one of provisioning and configuration of the network element wherein the one or more instructions cause the second processor to modify based on an identification of the second processor an execution flow of the exception to execute an interrupt handler located within a respective dedicated interrupt handling vector address spaces associated with the second processor.
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Accused Products
Abstract
A method and apparatus for exception handling in a multi-processor environment are described. In an embodiment, a method for handling a number of exceptions within a processor in a multi-processing system includes receiving an exception within the processor, wherein each processor in the multi-processor system shares a same memory. The method also includes executing a number of instructions at an address within a common interrupt handling vector address space of the same memory. The number of instructions cause the processor to determine an identification of the processor based on a query that is internal to the processor. Additionally, the method includes modifying execution flow of the exception to execute an interrupt handler located within one of a number of different interrupt handling vector address spaces.
21 Citations
13 Claims
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1. A network element for routing traffic between networks, compnsing:
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a first line card coupled to a first network; a second line card coupled to a second network different than the first network; a control card coupled to the first line card and the second line card for routing network traffic between the first and second networks via the first line card and the second line card, the control card including a plurality of processors including a first processor and a second processor, a memory including a common exception handling vector address space shared by the plurality of processors, and a plurality of exception handling vector address spaces each associated with each of the plurality of processors, including a first exception and a second exception handling vector address spaces associated with the first and second processors respectively, a memory controller coupled to the memory and the plurality of processors, wherein the first processor is to execute a first operating system, wherein the first operating system is a real-time operating system to handle routing network traffic, and wherein the second processor is to execute a second operating system and to execute one or more instructions in the common exception handling vector address space upon receipt of an exception, wherein the second operating system is a non-real-time operating system to handle at least one of provisioning and configuration of the network element wherein the one or more instructions cause the second processor to modify based on an identification of the second processor an execution flow of the exception to execute an interrupt handler located within a respective dedicated interrupt handling vector address spaces associated with the second processor. - View Dependent Claims (2)
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3. A system comprising:
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a plurality of processors to execute different operating systems and to each handle exceptions, wherein at least one of the different operating systems is a real-time operating system to handle routing network traffic and at least one other one of the different operating systems is a non-real-time operating system to handle at least one of provisioning and configuration of a network element; a memory device to store a common exception handling vector address space, the address space having a separate interrupt handler for each operating system; and a memory controller coupled to the memory and plurality of processors, wherein upon receiving an exception at one of the plurality of processors, the processor determines a type of the exception and executes instructions within the common exception handling vector address space to determine an identification of the processor based on a value in an internal register and to select an interrupt handler for the operating system of the identified processor. - View Dependent Claims (4, 5)
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6. A system to handle exceptions comprising:
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a plurality of processors; a plurality of dissimilar operating systems, wherein each of the plurality of processors executes one of the plurality of dissimilar operating systems, wherein at least some of the plurality of dissimilar operating systems are real-time operating systems to handle routing network traffic and at least some of the plurality of dissimilar operating systems are non-real-time operating systems to handle at least one of provisioning and configuration of a network element; a memory, wherein the memory is to store a common exception handling vector address space and a plurality of separate interrupt handlers for each of the plurality of dissimilar operating systems; and a memory controller coupled to the memory and the plurality of processors, wherein upon receiving an exception by one of the plurality of processors, the one of the plurality of processors determines a type of the exception, executes instructions within the common exception handling vector address space, determines an identification of the one of the plurality of processors based on a value stored in an internal register of the one of the plurality of processors, and selects one of a plurality of separate interrupt handlers for the operating system of the identified processor. - View Dependent Claims (7, 8, 9)
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10. A machine storage-readable medium that provides instructions to handle exceptions in a system having a plurality of processors, a plurality of dissimilar operating systems, a memory, and a memory controller coupled to the memory and the plurality of processors, the instructions when executed by a machine, causes the machine to perform operations comprising:
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receiving an exception within one of the plurality of processors, wherein each of the plurality of processors execute one of the plurality of dissimilar operating systems, the memory is used to store a common exception handling vector address space and a plurality of separate interrupt handlers for each of the plurality of dissimilar operating systems, the one of the plurality of processors having an internal register, wherein at least some of the plurality of dissimilar operating systems are real-time operating systems to handle routing network traffic and at least some of the plurality of dissimilar operating systems are non-real-time operating systems to handle at least one of provisioning and configuration of a network element; determining a type of the execution by the one of the plurality of processors; executing instructions within the common exception handling vector address space by the one of the plurality of processors; determining, by the one of the plurality of processors, an identification of the one of the plurality of processors based on a value stored in the internal register; and selecting one of a plurality of separate interrupt handlers for the operating system of the identified processor by the one of the plurality of processors. - View Dependent Claims (11, 12, 13)
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Specification