CMOS structures and methods using self-aligned dual stressed layers

• US 7,521,307 B2
• Filed: 04/28/2006
• Issued: 04/21/2009
• Est. Priority Date: 04/28/2006
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong, Yang, Daewon
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Kim; Sun M
• Application Number:
  US11/380,695
• Publication Number:
  US 20070252214A1
• Time in Patent Office: 1,089 Days
• Field of Search: 257/E21.633
• US Class Current: 438/199
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.

Claims

1. A method for fabricating a CMOS structure comprising:

forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate;

forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor, where the first stressed layer and the second stressed layer abut and overlap;

forming a blanket layer over the first stressed layer and the second stressed layer that abut and overlap;

further masking the blanket layer over the first stressed layer and the second stressed layer to leave uncovered at least the portion of the first stressed layer and the second stressed layer that abut and overlap; and

etching the blanket layer and at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.

2. The method of claim 1 further comprising forming a blocking layer over the first stressed layer and the second stressed layer prior to further masking has been deleted.

3. The method of claim 1 wherein the forming the first transistor and the second transistor uses a hybrid orientation substrate that provides a different crystallographic orientation channel for each of the first transistor and the second transistor.

4. The method of claim 1 wherein each of the first stressed layer and the second stressed layer comprises a nitride material.

5. The method of claim 1 wherein:

the first stress is a tensile stress and the first transistor is an nFET; and

the second stress is a compressive stress and the second transistor in a pFET.

6. The method of claim 1 wherein the etching provides that the first stressed layer and the second stressed layer abut but do not overlap over a source/drain region within one of the first transistor and the second transistor.