Resistance-based etch depth determination for SGT technology

• US 7,521,332 B2
• Filed: 03/23/2007
• Issued: 04/21/2009
• Est. Priority Date: 03/23/2007
• Status: Expired due to Fees

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Yu, Bhalla, Anup, Li, Tiesheng, Lou, Yingying
• Primary Examiner(s): Garber; Charles D.
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US11/690,581
• Publication Number:
  US 20080272371A1
• Time in Patent Office: 760 Days
• Field of Search: 438/386, 438/426, 438/725
• US Class Current: 438/426
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D_L of the test structure is determined from the signal and an etch depth D_T is determined from D_L. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

Claims

1. A method for determining etch depth, comprising:

a) forming a layer of material over a portion of a substrate having a trench formed thereon in such a way that the material fills the trench;

b) forming a mask over a test portion of the layer of material, wherein the mask does not cover the trench, wherein the mask defines a test structure that lies underneath a portion of the mask;

c) isotropically etching the layer of material;

d) measuring a signal related to a resistance change of the test structure during or after etching;

e) determining an amount of lateral undercut D_L of the test structure from the signal; and

f) determining an etch depth D_T of the material in the trench based on the amount of lateral undercut D_L.

2. The method of claim 1 wherein the test structure comprises a bar shape.

3. The method of claim 2 wherein the test structure comprises a polysilicon.

4. The method of claim 3 wherein step b) comprises defining a plurality of test structures that form resistors of a bridge circuit.

5. The method of claim 4 wherein the bridge circuit is a Wheatstone bridge circuit.

6. The method of claim 5 wherein the Wheatstone bridge circuit comprises first and second resistors at opposite arms of the Wheatstone bridge circuit.

7. The method of claim 6 wherein the Wheatstone bridge circuit comprises third and fourth resistors having larger resistances than the first and second resistors.

8. The method of claim 7 wherein a ratio length to width ratio L/W is the smaller for the first, second resistors than for the third and fourth resistors.

9. The method of claim 7 wherein resistances of first, second are the same and resistances of third and fourth resistors are the same.

10. The method of claim 1, further comprising, controlling the etch process in response to the signal.

11. A method of forming a shielded gate trench (SGT) structure, comprising:

a) filling a trench with polysilicon wherein a polysilicon film is formed over the trench;

b) placing a mask over the polysilicon film, wherein one or more polysilicon test structures are defined under a portion of the photoresist mask;

c) isotropically etching the polysilicon film, wherein the polysilicon in the trench is etched to an etch depth D_T;

d) measuring a signal related to a resistance of one or more of the polysilicon test structures during or after etching;

e) determining an amount of lateral undercut D_L of one or more of the polysilicon test structures based on the resistance; and

f) determining the etch depth D_T based on the length of the amount of lateral undercut D_L.

12. The method of claim 11, further comprising, controlling the etching in response to the signal.