Crack stop for low K dielectrics

• US 7,521,336 B2
• Filed: 10/31/2007
• Issued: 04/21/2009
• Est. Priority Date: 07/28/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Pouliot, Mark J., Daubenspeck, Timothy H., McDevitt, Thomas L., Luce, Stephen E., Motsiff, William T., Robbins, Jennifer C.
• Primary Examiner(s): Picardat; Kevin M
• Application Number:
  US11/931,194
• Publication Number:
  US 20080064189A1
• Time in Patent Office: 538 Days
• Field of Search: 438/68, 438/113, 438/114, 438/458, 438/460, 438462-465
• US Class Current: 438/462
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

Claims

1. A method of forming an integrated circuit chip, comprising the steps of:

forming an active circuit area on a substrate, said active circuit area including a plurality of metal layers separated by capping/etch stop layers;

forming a moisture barrier around said active circuit area;

forming a stack of metal interconnects and barrier layers outside said moisture barrier;

forming a top A1 layer over a portion of the IC chip; and

removing the stack of metal interconnects and barrier layers, using an Al selective process, to form an outer ring etched out region as a crack stop to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation performed on the IC chip.

2. A method according to claim 1, wherein the removing step includes the step of etching the IC chip in a wet etch that removes the stack of metal interconnects and barrier layers selective to Al, to form said outer ring etched out region.

3. The method of claim 2, wherein the etching stop includes the step of etching the IC chip in a wet etch comprising dilute H2S04:

H202;

HF.

4. The method of claim 2, wherein the etching step includes the step of etching the IC chip in a wet etch comprising dilute H2S04:

H202.

5. The method of claim 2, wherein the step of forming the metal interconnects includes the step of forming the metal interconnects as copper interconnects.

6. The method of claim 2, wherein the step of forming the metal interconnects includes the step of forming the metal interconnects as silver interconnects.