Interconnect structure encased with high and low k interlevel dielectrics

• US 7,521,359 B2
• Filed: 03/25/2008
• Issued: 04/21/2009
• Est. Priority Date: 05/09/2005
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H.
• Primary Examiner(s): Thai; Luan C
• Application Number:
  US12/054,681
• Publication Number:
  US 20080169572A1
• Time in Patent Office: 392 Days
• Field of Search: 438/216, 438/387, 438/667, 438/672
• US Class Current: 438/667
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device. The interconnect to the receiver, which does not carry a high current, is surrounded by a low-k material for reduced capacitance and performance advantages.

Claims

1. An integrated circuit apparatus, comprising:

an electrostatic discharge (ESD) device;

a pad; and

a wiring level on a substrate comprising;

an interconnect comprising a plurality of interconnect wires having a common electrical node electrically connecting said pad and said ESD device;

a high-k material substantially filling at least a region in between said interconnect wires, said region extending from a sidewall of one of said interconnect wires to a sidewall of an adjacent one of said interconnect wires, said high-k material for increasing an electrostatic discharge robustness of the interconnect; and

a low-k material adjacent to said interconnect and located outside of said region that is substantially filled by said high-k material for reducing a capacitance of the interconnect.

2. The integrated circuit apparatus according to claim 1, wherein said high-k material is also disposed above or below said interconnect wires.

3. The integrated circuit apparatus according to claim 1, wherein said high-k material surrounds said interconnect.

4. The integrated circuit apparatus according to claim 1, wherein said high-k material is disposed between said low-k material and said interconnect.

5. The integrated circuit apparatus according to claim 1, wherein said high-k material is SiO₂.

6. The integrated circuit apparatus according to claim 1, wherein said high-k material has a thickness equal to or greater than a thermal diffusion distance of said interconnect.

7. The integrated circuit apparatus according to claim 1, wherein said high-k material has a dielectric constant, k, of higher than about 3.5.

8. The integrated circuit apparatus according to claim 1, wherein said high-k material has a dielectric constant, k, of about 4.0.

9. The integrated circuit apparatus according to claim 1, wherein said low-k material has a dielectric constant, k, of lower than about 3.5.

10. An interconnect structure, comprising:

a metal conductor comprising a plurality of interconnect wires having a common electrical node in a wiring level on a substrate;

a high-k material substantially filling at least a region in between said interconnect wires, said region extending from a sidewall of one of said interconnect wires to a sidewall of an adjacent one of said interconnect wires, said high-k material for increasing an electrostatic discharge robustness of the interconnect structure; and

a low-k material adjacent to said metal conductor and located outside of said region that is substantially filled by said high-k material for reducing a capacitance of the interconnect structure.

11. The interconnect structure according to claim 10, wherein said metal conductor comprises a damascene copper interconnect wire or a dual damascene copper interconnect wire and via structure.

12. The interconnect structure according to claim 10, wherein said high-k material is disposed between said low-k material and said metal conductor.