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Interconnect structure encased with high and low k interlevel dielectrics

  • US 7,521,359 B2
  • Filed: 03/25/2008
  • Issued: 04/21/2009
  • Est. Priority Date: 05/09/2005
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit apparatus, comprising:

  • an electrostatic discharge (ESD) device;

    a pad; and

    a wiring level on a substrate comprising;

    an interconnect comprising a plurality of interconnect wires having a common electrical node electrically connecting said pad and said ESD device;

    a high-k material substantially filling at least a region in between said interconnect wires, said region extending from a sidewall of one of said interconnect wires to a sidewall of an adjacent one of said interconnect wires, said high-k material for increasing an electrostatic discharge robustness of the interconnect; and

    a low-k material adjacent to said interconnect and located outside of said region that is substantially filled by said high-k material for reducing a capacitance of the interconnect.

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