Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby

• US 7,521,360 B2
• Filed: 10/10/2006
• Issued: 04/21/2009
• Est. Priority Date: 04/09/2003
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Halahan, Patrick A., Lan, Bosco, Kao, Sam, Savastiouk, Sergey, Siniaguine, Oleg
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US11/548,053
• Publication Number:
  US 20070128868A1
• Time in Patent Office: 924 Days
• Field of Search: 438/667, 438/671, 438/674, 438/678, 438/977, 257/E21.597, 257/E23.011
• US Class Current: 438/678
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole'"'"'s sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening'"'"'s sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

Claims

1. A manufacturing method comprising:

forming an opening in a first surface of a body comprising a semiconductor substrate, wherein the opening extends into the semiconductor substrate;

forming a seed for electroplating a conductor into the opening;

electroplating the conductor into the opening, wherein the electroplating is initiated on the seed at a distance from the first surface of the body but not over the opening'"'"'s sidewalls adjacent the first surface of the body, wherein before the electroplating operation, a through hole is formed in the semiconductor substrate at the location of the opening; and

forming a conductive layer over a second surface of the body;

wherein forming the opening and the through hole comprises;

forming the opening in the first surface of the body such that the opening does not go through the body;

after forming the conductive layer, extending the opening to form the through hole and expose the conductive layer from the first surface of the body;

wherein the seed electrically contacts the conductive layer in the opening;

wherein the method further comprises coupling the conductive layer to an electrical potential for the electroplating operation, wherein during the electroplating operation the seed is coupled to the electrical potential through the conductive layer.

2. The method of claim 1 wherein forming the opening comprises extending the opening into a first surface of the semiconductor substrate, and the electroplating is initiated at a distance from the first surface of the semiconductor substrate but not over the opening'"'"'s sidewalls adjacent the first surface of the semiconductor substrate.

3. The method of claim 1 wherein the seed is spaced from the first surface of the body.

4. The method of claim 1 wherein forming the opening and the seed comprises:

obtaining the body; and

then

forming the seed on the body.

5. The method of claim 1 wherein the body comprises a transistor.

6. The method of claim 1 wherein the body comprises a diode.

7. The method of claim 1 wherein after the electroplating operation a contact pad is present at a second surface of the body at the through hole'"'"'s location, the contact pad having a first surface facing away from the body, the contact pad'"'"'s first surface being exposed and comprising at least a portion of the seed and/or the conductor and/or a conductive layer physically contacting the seed and/or the conductor, the contact pad'"'"'s first surface not being attached to any circuit external to the body.

8. The method of claim 7 further comprising attaching the contact pad'"'"'s first surface to a circuit located outside of the body.