Integrated circuit devices having active regions with expanded effective widths

• US 7,521,753 B2
• Filed: 01/29/2007
• Issued: 04/21/2009
• Est. Priority Date: 10/28/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kang-yoon, Park, Jong-woo
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US11/699,142
• Publication Number:
  US 20070120183A1
• Time in Patent Office: 813 Days
• Field of Search: 257/374, 257/329, 257/330
• US Class Current: 257/329
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

An integrated circuit device includes a substrate having a trench formed therein. An isolation layer is disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench. A buffer layer is disposed between the isolation layer and the trench. A gate insulating layer is disposed on the second sidewall portion of the trench and extends onto the substrate adjacent to the trench.

Claims

1. An integrated circuit device, comprising:

a substrate having a trench formed therein;

an isolation layer disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench;

a buffer layer disposed between the isolation layer and the substrate in the trench;

a channel region that is formed under a surface of the second sidewall portion of the trench and an upper surface of the substrate, wherein the channel region extends in a first direction along the substrate a distance exceeding a maximum depth of the channel region under the surface of the second sidewall portion of the trench and along the second sidewall portion of the trench a distance exceeding a maximum depth of the channel region under the upper surface of the substrate; and

a gate insulating layer disposed on the second sidewall portion of the trench and extending onto the substrate adjacent to the trench without extending onto the isolation layer.

2. The integrated circuit device of claim 1, wherein a length of the second sidewall portion is from approximately 150 Å

to approximately 500 Å

.

3. The integrated circuit device of claim 1, wherein a ratio of a length of the second sidewall portion to that of a length of the first sidewall portion is about ⅕

.

4. The integrated circuit device of claim 1, wherein the channel region does not extend under a lower portion of a surface of the first sidewall portion.

5. The integrated circuit device of claim 1, wherein the channel region has a substantially uniform depth.

6. The integrated circuit device of claim 1, wherein the channel region extends in a second direction different from the first direction between drain/source regions.

7. An integrated circuit device, comprising:

a substrate having a trench formed therein;

an isolation layer disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench;

a buffer layer disposed between the isolation layer and the substrate in the trench;

an impurity layer that is formed under a surface of the second sidewall portion of the trench and an upper surface of the substrate, wherein the impurity layer extends in a first direction along the substrate a distance exceeding a maximum depth of the impurity layer under the surface of the second sidewall portion of the trench and along the second sidewall portion of the trench a distance exceeding a maximum depth of the impurity layer under the upper surface of the substrate; and

a gate insulating layer disposed on the second sidewall portion of the trench and extending onto the substrate adjacent to the trench without extending onto the isolation layer.

8. The integrated circuit device of claim 7, wherein a length of the second sidewall portion is from approximately 150 Å

to approximately 500 Å

.

9. The integrated circuit device of claim 7, wherein a ratio of a length of the second sidewall portion to that of a length of the first sidewall portion is about ⅕

.

10. The integrated circuit device of claim 7, wherein the impurity layer does not extend under a lower portion of a surface of the first sidewall portion.

11. The integrated circuit device of claim 7, wherein the impurity layer has a substantially uniform depth.

12. The integrated circuit device of claim 7, wherein the impurity layer extends in a second direction different from the first direction between drain/source regions.