Post passivation interconnection schemes on top of the IC chips

• US 7,521,805 B2
• Filed: 10/23/2007
• Issued: 04/21/2009
• Est. Priority Date: 10/12/2004
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Picardat; Kevin M
• Application Number:
  US11/877,658
• Publication Number:
  US 20080042297A1
• Time in Patent Office: 546 Days
• Field of Search: 257/690, 257/700, 257/691, 257/920, 257/773, 257/774, 438614-616, 438/622, 438/631, 438/637, 438/638
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

an off-chip driver, receiver or I/O circuit in or on said silicon substrate;

an intra-chip driver or receiver in or on said silicon substrate;

an internal circuit in or on said silicon substrate, wherein said internal circuit comprises a MOS device;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said off-chip driver, receiver or I/O circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said off-chip driver, receiver or I/O circuit;

a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said intra-chip driver or receiver;

a fourth interconnecting structure connecting a second terminal of said intra-chip driver or receiver to said internal circuit;

a passivation layer over said dielectric layer;

a first via in said passivation layer, wherein said first via is connected to said second interconnecting structure;

a second via in said passivation layer, wherein said second via is connected to said third interconnecting structure;

a fifth interconnecting structure over said passivation layer, wherein said fifth interconnecting structure is connected to said first and second vias, wherein said second terminal of said off-chip driver, receiver or I/O circuit is connected to said first terminal of said intra-chip driver or receiver through, in sequence, said second interconnecting structure, said first via, said fifth interconnecting structure, said second via and said third interconnecting structure, and wherein said fifth interconnecting structure comprises a metal line having a sheet resistance of smaller than 7 milliohms per square, wherein said metal line comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer and an electroplated metal layer on said seed layer, wherein the material of said electroplated metal layer is the same as that of said seed layer, wherein said electroplated metal layer has a thickness between 2 and 100 micrometers, and wherein an undercut with an edge of said adhesion/barrier layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers; and

an external connection point connected to said first terminal of said off-chip driver, receiver or I/O circuit through said first interconnecting structure.

2. The integrated circuit chip of claim 1, wherein said adhesion/barrier layer comprises titanium.

3. The integrated circuit chip of claim 1, wherein said metal line has a width greater than 2 micrometers.

4. The integrated circuit chip of claim 1, wherein said electroplated metal layer comprises electroplated gold.

5. The integrated circuit chip of claim 1, wherein said electroplated metal layer comprises electroplated copper.

6. The integrated circuit chip of claim 1, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

7. The integrated circuit chip of claim 1, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

8. An integrated circuit chip comprising:

a silicon substrate;

an ESD circuit in or on said silicon substrate;

an driver, receiver or I/O circuit in or on said silicon substrate;

an internal circuit in or on said silicon substrate, wherein said internal circuit comprises a MOS device;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit and to a first terminal of said driver, receiver or I/O circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said driver, receiver or I/O circuit;

a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said internal circuit;

a passivation layer over said dielectric layer;

a first via in said passivation layer, wherein said first via is connected to said second interconnecting structure;

a second via in said passivation layer, wherein said second via is connected to said third interconnecting structure;

a fourth interconnecting structure over said passivation layer, wherein said fourth interconnecting structure is connected to said first and second vias, wherein said second terminal of said driver, receiver or I/O circuit is connected to said internal circuit through, in sequence, said second interconnecting structure, said first via, said fourth interconnecting structure, said second via and said third interconnecting structure, and wherein said fourth interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said metal line comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer and an electroplated metal layer on said seed layer, wherein the material of said electroplated metal layer is the same as that of said seed layer, wherein said electroplated metal layer has a thickness between 2 and 100 micrometers, and wherein an undercut with an edge of said adhesion/barrier layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers; and

an external connection point connected to said ESD circuit and to said first terminal of said driver, receiver or I/O circuit through said first interconnecting structure.

9. The integrated circuit chip of claim 8, wherein said adhesion/barrier layer comprises titanium.

10. The integrated circuit chip of claim 8, wherein said metal line has a width greater than 2 micrometers.

11. The integrated circuit chip of claim 8, wherein said electroplated metal layer comprises electroplated gold.

12. The integrated circuit chip of claim 8, wherein said electroplated metal layer comprises electroplated copper.

13. The integrated circuit chip of claim 8, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

14. The integrated circuit chip of claim 8, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

15. An integrated circuit chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate, wherein said first internal circuit comprises a MOS device;

a second internal circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a signal node of said first internal circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers;

a polymer layer on said passivation layer;

a first via in said polymer layer, wherein said first via is connected to said first interconnecting structure;

a second via in said polymer layer, wherein said second via is connected to said second interconnecting structure; and

a third interconnecting structure over said passivation layer and in said polymer layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said signal node of said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, and wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said metal line comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer and an electroplated metal layer on said seed layer, wherein the material of said electroplated metal layer is the same as that of said seed layer, wherein said electroplated metal layer has a thickness between 2 and 100 micrometers, and wherein an undercut with an edge of said adhesion/barrier layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers.

16. The integrated circuit chip of claim 15, wherein said adhesion/barrier layer comprises titanium.

17. The integrated circuit chip of claim 15, wherein said metal line has a width greater than 2 micrometers.

18. The integrated circuit chip of claim 15, wherein said electroplated metal layer comprises electroplated gold.

19. The integrated circuit chip of claim 15, wherein said electroplated metal layer comprises electroplated copper.

20. The integrated circuit chip of claim 15, wherein said adhesion/barrier layer comprises titanium nitride.