High-speed level-shifting circuit

• US 7,521,964 B1
• Filed: 03/26/2007
• Issued: 04/21/2009
• Est. Priority Date: 03/26/2007
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ho, Vinh Van, Luo, Mei
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/691,106
• Time in Patent Office: 757 Days
• Field of Search: 326/63, 326/68, 326/81, 326/115, 327/333
• US Class Current: 326/68
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

In level-shifting circuitry for shifting low-voltage-domain signals to a high-voltage domain, one of two output transistors is driven with one of the low-voltage-domain signals, thereby reducing loading on the output and increasing output speed and bandwidth. The circuitry can be mirrored for differential operation. When included in a serial interface of a programmable logic device, the circuitry can be programmably selectable between single-ended and differential operation.

Claims

1. A level-shifting circuit for accepting an input signal at a first power-supply level and providing said input signal as an output signal at a second power-supply level higher than said first power-supply level, said level-shifting circuit comprising:

a first power supply at said first power-supply level;

a second power supply at said second power-supply level;

a first complementary transistor pair arranged as an inverter between said first power supply and ground, accepting as an input said input signal, and providing as a first intermediate signal said input signal inverted;

a second complementary transistor pair connected in source-to-drain configuration between said second power supply and said first intermediate signal, a first transistor of said second complementary transistor pair being gated by a reference signal and a second transistor of said second complementary transistor pair being gated by said input signal, said second complementary transistor pair providing a second intermediate output at their common connection; and

a third complementary transistor pair arranged in source-to-drain configuration between said second power supply and ground, a first transistor of said third complementary transistor pair being gated by said first intermediate signal and a second transistor of said third complementary transistor pair being gated by said second intermediate signal, said third complementary transistor pair providing said output signal at their common connection.

2. The level-shifting circuit of claim 1 wherein said reference signal is provided by a bias current generator and a diode in series between said second power supply and said first power supply.

3. The level-shifting circuit of claim 1 wherein each of said complementary transistor pairs comprises a respective n-channel transistor and a respective p-channel transistor.

4. The level-shifting circuit of claim 3 wherein:

in said second complementary transistor pair, said first transistor is said n-channel device and said second transistor is said p-channel device; and

in said third complementary transistor pair, said first transistor is said p-channel device and said second transistor is said n-channel device.

5. The level-shifting circuit of claim 1 comprising two each of said first complementary transistor pair, said second complementary transistor pair and said third complementary transistor pair;

wherein;

one each of said first, second and third complementary transistor pairs are connected as defined by claim 1 to form a first differential portion;

another one each of said first, second and third complementary transistor pairs are connected as defined by claim 1 to form a second differential portion;

said first and second differential portions share said first power supply, said second power supply and said reference signal;

said inputs of said first and second differential portions form differential inputs of said level-shifting circuit; and

said outputs of said first and second differential portions form differential outputs of said level-shifting circuit.

6. A programmable logic device comprising a serial interface having a level-shifting circuit as defined in claim 5.

7. The programmable logic device of claim 6 wherein said level-shifting circuit is programmably selectable between being single-ended and being differential.

8. The programmable logic device of claim 7 wherein one of said first and second differential portions is programmably disconnectable from said level-shifting circuit.

9. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 7 coupled to the processing circuitry and the memory.

10. A printed circuit board on which is mounted a programmable logic device as defined in claim 7.

11. The printed circuit board defined in claim 10 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

12. The printed circuit board defined in claim 11 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

13. A differential level-shifting circuit for accepting a differential input signal at a first power-supply level and providing said input signal as an output signal at a second power-supply level higher than said first power-supply level, said differential level-shifting circuit comprising:

a first power supply at said first power-supply level;

a second power supply at said second power-supply level; and

first and second differential level-shifting portions, each of said first and second differential level-shifting portions comprising;

a first complementary transistor pair arranged as an inverter between said first power supply and ground, accepting as an input said input signal, and providing as a first intermediate signal said input signal inverted,

a second complementary transistor pair connected in source-to-drain configuration between said second power supply and said first intermediate signal, a first transistor of said second complementary transistor pair being gated by a reference signal and a second transistor of said second complementary transistor pair being gated by said input signal, said second complementary transistor pair providing a second intermediate output at their common connection, and

a third complementary transistor pair arranged in source-to-drain configuration between said second power supply and ground, a first transistor of said third complementary transistor pair being gated by said first intermediate signal and a second transistor of said third complementary transistor pair being gated by said second intermediate signal, said third complementary transistor pair providing said output signal at their common connection;

wherein;

said inputs of said first and second differential level-shifting portions form differential inputs of said level-shifting circuit; and

said outputs of said first and second differential portions form differential outputs of said level-shifting circuit.

14. The differential level-shifting circuit of claim 13 wherein said first and second differential level-shifting portions share said first power supply, said second power supply and said reference signal.

15. The differential level-shifting circuit of claim 13 wherein said reference signal is provided by a bias current generator and a diode in series between said second power supply and said first power supply.

16. The differential level-shifting circuit of claim 15 wherein said first and second differential level-shifting portions share said first power supply, said second power supply, said bias current generator and said diode.

17. The differential level-shifting circuit of claim 13 wherein each of said complementary transistor pairs comprises a respective n-channel transistor and a respective p-channel transistor.

18. The differential level-shifting circuit of claim 17 wherein:

in said second complementary transistor pair, said first transistor is said n-channel device and said second transistor is said p-channel device; and

in said third complementary transistor pair, said first transistor is said p-channel device and said second transistor is said n-channel device.

19. A level-shifting circuit for accepting an input signal at a first power-supply level and providing said input signal as an output signal at a second power-supply level higher than said first power-supply level, said level-shifting circuit comprising:

input circuitry operating in a low-power domain at said first power supply level, said input circuitry accepting said input signal and providing a low-power domain output signal that is substantially inverse to said input signal; and

output circuitry operating in a high-power domain between said second power supply level and said low-power domain output signal, said output circuitry accepting said input signal and said low-power domain output signal to provide an intermediate high-power domain signal, said output circuitry having a final output stage gated by said intermediate high-power domain signal and by said low-power domain output signal.

20. The level-shifting circuit of claim 19 further comprising:

a first power supply at said first power-supply level;

a second power supply at said second power-supply level;

a reference signal generator between said second power supply and said first power supply.

21. The level-shifting circuit of claim 20 wherein said reference signal generator comprises a bias current generator and a diode.

22. The level-shifting circuit of claim 20 wherein:

said input circuitry is mirrored to provide differential inputs to said level-shifting circuit; and

said output circuitry is mirrored to provide differential outputs of said level-shifting circuit.

23. A programmable logic device comprising a serial interface having a level-shifting circuit as defined in claim 19.

24. The programmable logic device of claim 23 wherein said level-shifting circuit is programmably selectable between being single-ended and being differential.

25. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 24 coupled to the processing circuitry and the memory.

26. A printed circuit board on which is mounted a programmable logic device as defined in claim 19.

27. The printed circuit board defined in claim 26 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

28. The printed circuit board defined in claim 27 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.