Low power high speed latch for a prescaler divider

• US 7,521,976 B1
• Filed: 12/07/2005
• Issued: 04/21/2009
• Est. Priority Date: 12/08/2004
• Status: Active Grant

• Current Assignee: Shen Realty
• Original Assignee: NanoAmp Solutions Incorporated
• Inventors: Shen, David H., Sudjian, Douglas
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US11/296,549
• Time in Patent Office: 1,231 Days
• Field of Search: 331/1.A, 331/16, 331/25, 327/185, 327/199, 327/200, 327/201, 327/208, 327210-212, 327/223
• US Class Current: 327/199
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

Claims

1. A prescaler circuit comprising:

a latch comprising;

a first clocked differential pair comprising input terminals coupled to a data input of the latch, a first output terminal coupled to a first output of the latch, and a second output terminal coupled to a second output of the latch;

a second clocked differential pair with a first input terminal coupled to the second output of the latch, a second input terminal coupled to the first output of the latch;

a first output terminal coupled to the first output of the latch, and a second output terminal coupled to the second output of the latch;

a first shunt peaked active load circuit coupled to the first output of the latch;

a second shunt peaked active load circuit connected to the second output of the latch;

a replica bias circuit to control a voltage of the shunt peaked active loads, wherein the replica bias circuit comprises a transistor stack to replicate a voltage drop across the shunt peaked active loads of the latch, wherein the shunt peaked active loads comprise a resistor and a transistor; and

wherein the replica bias circuit is configured to generate a voltage at the resistors that is higher than a supply voltage of the latch; and

a filter network coupled between the replica bias circuit and the resistors.

2. The prescaler circuit of claim 1, wherein the filter network comprises a filter capacitor to establish an AC ground potential at a node coupled to the resistors, wherein the filter capacitor comprises a gate capacitance of a transistor with a source terminal and drain terminal connected together.

3. The prescaler circuit of claim 2 wherein the filter network further comprises a bias resistor that is coupled between the replica bias circuit and the resistors of the shunt peaked active loads.

4. The prescaler circuit of claim 3, wherein a response speed of the shunt peaked active load circuits is a factor of the voltage controlled with the replica bias circuit.

5. The prescaler circuit of claim 4, wherein the bias resistor is coupled to a gate of the transistor that comprises the gate capacitance.

6. The prescaler circuit of claim 5, wherein the replica bias circuit comprises a feedback amplifier that compensates for process and temperature variations, and wherein the voltage controlled with the replica bias circuit is coupled to the output of the feedback amplifier.

7. The prescaler circuit of claim 5, wherein one transistor in the transistor stack is biased at a common mode voltage of the latch plus one half of a differential voltage of latch clocks.

8. The prescaler circuit of claim 1, wherein the latch is configured as a differential amplifier circuit.

9. The prescaler circuit of claim 1, wherein the latch is configured as used in a divider circuit.

10. The prescaler circuit at of claim 1, wherein the latch is configured to be implemented in semiconductor technologies comprising CMOS, bipolar, BiCMOS, SiGe, and GaAs technologies.

11. A prescaler circuit comprising:

a latch with an active load configured for shunt-peaked amplification, wherein the active load comprises shunt-peaking elements configured to have an inductive impedance that at least partially cancel a capacitive load impedance of the latch, the latch further comprising resistors coupled to the shunt-peaking elements;

a replica bias circuit configured to control a voltage of the shunt-peaking elements, wherein the replica bias circuit comprises a transistor stack to replicate a voltage drop across the shunt-peaking elements of the latch, and wherein the replica bias circuit is configured to generate a voltage at the resistors that is higher than a supply voltage of the latch; and

a filter network coupled between the replica bias circuit and the resistors.

12. The prescaler circuit of claim 11, wherein the shunt-peaking elements comprise inductorless elements.

13. The prescaler circuit of claim 11, wherein the latch comprises a current-mode logic (CML) latch, and wherein a replica bias circuit current is a scaled version of a latch current.

14. The prescaler circuit of claim 11, wherein the latch comprises two flip flips.

15. The prescaler circuit of claim 11, wherein the active load comprises transistors, wherein a gain of the latch is a function of a ratio of transconductances of the transistors.

16. The prescaler circuit of claim 15, wherein the transistors comprise gate widths and lengths that are scaled for the transistors to serve as inductive active load elements.

17. The prescaler circuit of claim 16, wherein source nodes of the transistors are configured to have a voltage controlled with the voltage generated from the replica bias circuit.

18. The prescaler circuit of claim 16, wherein the transistors comprises shunt impedance values that approximate a spiral inductor impedance.

19. A method to improve a bandwidth of a latch, the method comprising:

generating an inductive impedance in the latch with inductorless loads in the latch, wherein the inductorless loads comprise resistors and transistors as shunt-peaking elements, and wherein the transistors have a port that appears as the inductive impedance;

tuning a frequency of the latch by using the inductive impedance of the inductorless loads to at least partially cancel a capacitive load impedance of the latch;

adjusting a timing requirement of the latch with the tuned frequency to provide the improvement of the bandwidth;

biasing the inductorless loads with a replica bias circuit voltage comprising a voltage that is higher than a supply voltage of the latch; and

filtering the replica bias circuit voltage with a filtering network coupled to the inductorless loads.

20. The method of claim 19, wherein the latch is a current-mode logic (CML) latch.

21. The method of claim 19, further comprising employing the latch as a prescaler for a divider circuit.

22. The method of claim 21, further comprising setting a gain of the divider circuit as a function of a ratio of tranconductances of the transistors.

23. The method of claim 19, wherein the adjustment of the timing requirement comprises adjusting a setup time requirement or a hold time requirement of the latch.

24. The method of claim 19, further comprising clocking the latch at a clocking frequency that is a function of the frequency tuning of the latch.

25. A prescaler circuit comprising:

at least two latches coupled together to form a flip flop circuit such that when a first latch is in a first mode, a second latch is in an opposite mode, wherein the first mode is either a sample mode or a hold mode;

a pair of transistors in at least one of the latches to form a shunt-peaked load in the latch, the pair of transistors being configured to form an inductive impedance to partially cancel a capacitive load impedance of the latch;

a bias circuit to generate a bias voltage for the pair of transistors; and

a filter network coupled between the bias circuit and the pair of transistors to filter the bias voltage.

26. The prescaler circuit of claim 25, wherein the at least one latch comprises:

a clocking differential input pair of transistors configured to receive a differential input clock signal;

a differential input pair of transistors configured to receive a differential input data signal, the second differential input pair of transistors being coupled to a first transistor in the clocking differential input pair of transistors, the second differential input pair of transistors further being coupled to the pair of transistors that form the shunt-peaked loading; and

a differential output pair of transistors configured for a differential output signal, the differential output pair of transistors being coupled to a second transistor in the clocking differential input pair of transistors, the differential output pair of transistors being coupled to the pair of transistors that form the shunt-peaked loading, the differential output pair of transistors further being crossed-coupled to the differential input pair of transistors.

27. The prescaler circuit of claim 25, wherein the at least one latch comprises a current-mode logic (CML) latch, and wherein the bias circuit comprises a transistor stack that is configured to replicate a voltage drop across the pair of transistors in the latch.

28. The prescaler circuit of claim 25, wherein the bias circuit is configured for lower speed operation than the at least one latch, and wherein the filter network comprises a capacitor to establish an AC ground potential for the pair of transistors.

29. The prescaler circuit of claim 25, wherein the inductive impedance in the at least one latch at least partially cancels out a capacitance load impedance of the at least one latch.

30. The prescaler circuit of claim 29, wherein the at least one latch is configured to reduce an amount of a switching current when the inductive impedance at least partially cancels out the capacitance load impedance.

31. The prescaler circuit of claim 30, wherein an impedance at sources of the pair of transistors in the at least one latch comprises the inductive impedance in the latch.