DRAM power bus control

• US 7,522,466 B2
• Filed: 05/14/2007
• Issued: 04/21/2009
• Est. Priority Date: 08/23/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Raad, George B
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/803,444
• Publication Number:
  US 20080031071A1
• Time in Patent Office: 708 Days
• Field of Search: 365/226, 365/222, 365/228, 365/206
• US Class Current: 365/226
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Claims

1. A method of controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said method comprising:

powering a delay lock loop circuit with a first voltage;

powering reads and writes of said array with a second voltage; and

powering reads and writes for a finite period of time during said periodic refreshing of said array with a third voltage, wherein said third voltage is higher than said second voltage.

2. The method of claim 1 further comprising at least one of:

regulating said first voltage; and

regulating said second voltage.

3. The method of claim 1 wherein said first voltage and said second voltage are different.

4. The method of claim 1 further comprising:

receiving said first voltage from a first integrated circuit chip power pad; and

receiving said second voltage from a second integrated circuit chip power pad.

5. The method of claim 4 further comprising receiving said third voltage from said second integrated circuit chip power pad and a third integrated circuit chip power pad for said finite period of time during said periodic refreshing of said array.

6. The method of claim 4 further comprising receiving said third voltage from said first integrated circuit chip power pad and said second integrated circuit chip power pad for said finite period of time during said periodic refreshing of said array.

7. The method of claim 1 wherein before said powering reads and writes for a finite period of time:

refreshing said dynamic random access memory in order to maintain stored values; and

after said powering reads and writes for a finite period of time;

powering reads and writes of said array with said second voltage prior to completion to said refreshing.

8. The method of claim 1 further comprising powering an electrostatic discharge device with said second voltage.