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DRAM power bus control

  • US 7,522,466 B2
  • Filed: 05/14/2007
  • Issued: 04/21/2009
  • Est. Priority Date: 08/23/2002
  • Status: Expired due to Fees
First Claim
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1. A method of controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said method comprising:

  • powering a delay lock loop circuit with a first voltage;

    powering reads and writes of said array with a second voltage; and

    powering reads and writes for a finite period of time during said periodic refreshing of said array with a third voltage, wherein said third voltage is higher than said second voltage.

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