System having a controller device, a buffer device and a plurality of memory devices

• US 7,523,248 B2
• Filed: 01/11/2008
• Issued: 04/21/2009
• Est. Priority Date: 01/05/2000
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Perego, Richard E, Tsern, Ely
• Primary Examiner(s): Verbrugge; Kevin
• Application Number:
  US12/013,160
• Publication Number:
  US 20080109596A1
• Time in Patent Office: 466 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.

Claims

1. A memory system, comprising:

an integrated circuit master device;

a first memory module, the first memory module including;

a first integrated circuit buffer device, and

a first plurality of integrated circuit memory devices to store data received from the first integrated circuit buffer device;

a first plurality of signal lines between the first integrated circuit buffer device and the first plurality of integrated circuit memory devices, wherein the first plurality of signal lines includes a signal line to carry a source synchronous signal that has a predetermined temporal relationship with the data as the data is transferred between the first integrated circuit buffer device and the first plurality of integrated circuit memory devices;

a first point-to-point link between the integrated circuit master device and the first integrated circuit buffer device, wherein the first point-to-point link transfers data, address, and control information between the integrated circuit master device and the first integrated circuit buffer device; and

a second memory module, the second memory module including;

a second integrated circuit buffer device, and

a second plurality of integrated circuit memory devices to store data received from the second integrated circuit buffer device; and

a second point-to-point link between the integrated circuit master device and the second integrated circuit buffer device, wherein the second point-to-point link transfers data, address, and control information between the integrated circuit master device and the second integrated circuit buffer device.

2. The memory system of claim 1, further comprising:

a third memory module, the third memory module including;

a third integrated circuit buffer device, and

a third plurality of integrated circuit memory devices to store data received from the third integrated circuit buffer device; and

a third point-to-point link between the third integrated circuit buffer device and the second integrated circuit buffer device.

3. The memory system of claim 1, wherein the integrated circuit master device includes a processor.

4. The memory system of claim 1, wherein the integrated circuit master device includes a memory controller.

5. The memory system of claim 1, wherein the first plurality of signal lines includes at least one of a control line, a data line, and at least one device select line to select at least one integrated circuit memory device from the first plurality of integrated circuit memory devices.

6. The memory system of claim 5, wherein each signal line of the first plurality of signal lines includes a termination.

7. The memory system of claim 6, wherein the first memory module further includes:

a third plurality of integrated circuit memory devices to store data received from the first integrated circuit buffer device; and

a second plurality of signal lines between the first integrated circuit buffer device and the second plurality of integrated circuit memory devices.

8. The memory system of claim 1, wherein:

the first integrated circuit buffer device includes a first termination to terminate a first end of the first point-to-point link; and

the integrated circuit master device includes a second termination to terminate a second end of the first point-to-point link.

9. The memory system of claim 1, wherein the first integrated circuit buffer device includes a write buffer to hold data to be provided to at least one integrated circuit memory device of the first plurality of integrated circuit memory devices.

10. The memory system of claim 1, wherein each integrated circuit memory device of the first plurality of integrated circuit memory devices includes a dynamic random access memory cell array.

11. The memory system of claim 1, wherein the first point-to-point link includes a bi-directional link.

12. The memory system of claim 1, wherein the first point-to-point link includes a uni-directional link.

13. A memory system, comprising:

an integrated circuit master device;

a first integrated circuit buffer device;

a first plurality of integrated circuit memory devices to store data received from the first integrated circuit buffer device;

a first point-to-point link between the integrated circuit master device and the first integrated circuit buffer device, wherein the first point-to-point link transfers data, address, and control information between the integrated circuit master device and the first integrated circuit buffer device;

a second integrated circuit buffer device;

a second plurality of integrated circuit memory devices to store data received from the second integrated circuit buffer device;

a second point-to-point link between the first integrated circuit buffer device and the second integrated circuit buffer device;

a third integrated circuit buffer device;

a third plurality of integrated circuit memory devices to store data received from the third integrated circuit buffer device; and

a third point-to-point link between the integrated circuit master device and the third integrated circuit buffer device, wherein the third point-to-point link transfers data, address, and control information between the integrated circuit master device and the third integrated circuit buffer device.

14. The memory system of claim 13, wherein:

the first integrated circuit buffer device and the first plurality of integrated circuit memory devices are disposed on a first substrate;

the second integrated circuit buffer device and the second plurality of integrated circuit memory devices are disposed on a second substrate; and

the third integrated circuit buffer device and the third plurality of integrated circuit memory devices are disposed on a third substrate.

15. A memory system, comprising:

a first integrated circuit buffer device;

a first plurality of integrated circuit memory devices to store first data received from the first integrated circuit buffer device;

a first point-to-point link to provide the first data, address information associated with the first data, and control information associated with the first data to the first integrated circuit buffer device;

a second integrated circuit buffer device;

a second plurality of integrated circuit memory devices to store second data received from the second integrated circuit buffer device;

a second point-to-point link between the first integrated circuit buffer device and the second integrated circuit buffer device;

a third integrated circuit buffer device;

a third plurality of integrated circuit memory devices to store third data received from the third integrated circuit buffer device; and

a third point-to-point link to provide third data, address information associated with the third data, and control information associated with the third data to the third integrated circuit buffer device.

16. A memory system, comprising:

a first memory module, the first memory module including;

a first integrated circuit buffer device, and

a first plurality of integrated circuit memory devices for storing data received from the first integrated circuit buffer device;

a first point-to-point link for transferring data, address, and control information to the first integrated circuit buffer device;

a second memory module, the second memory module including;

a second integrated circuit buffer device, and

a second plurality of integrated circuit memory devices for storing data received from the second integrated circuit buffer device;

a second point-to-point link for transferring data, address, and control information to the second integrated circuit buffer device;

a third memory module, the third memory module including;

a third integrated circuit buffer device, and

a third plurality of integrated circuit memory devices for storing data received from the third integrated circuit buffer device; and

a third point-to-point link between the third integrated circuit buffer device and the second integrated circuit buffer device.

17. The memory system of claim 16, wherein the first memory module further includes a first plurality of signal lines between the first integrated circuit buffer device and the first plurality of integrated circuit memory devices, wherein the first plurality of signal lines includes at least one of a control line, a data line, a clock line, and at least one device select line, wherein the at least one device select line selects at least one integrated circuit memory device from the first plurality of integrated circuit memory devices.

18. A memory system, comprising:

a first integrated circuit buffer device;

a first plurality of integrated circuit memory devices to store data received from the first integrated circuit buffer device;

a first point-to-point link to transfer data, address, and control information to the first integrated circuit buffer device;

a second integrated circuit buffer device;

a second plurality of integrated circuit memory devices to store data received from the second integrated circuit buffer device;

a second point-to-point link to transfer data, address, and control information to the second integrated circuit buffer device;

a third integrated circuit buffer device;

a third plurality of integrated circuit memory devices to store data received from the third integrated circuit buffer device; and

a third point-to-point link between the third integrated circuit buffer device and the second integrated circuit buffer device.

19. The memory system of claim 18, further comprising:

a third plurality of integrated circuit memory devices to store data received from the first integrated circuit buffer device;

a third plurality of signal lines between the first integrated circuit buffer device and the third plurality of integrated circuit memory devices;

a fourth plurality of integrated circuit memory devices to store data received from the second integrated circuit buffer device; and

a fourth plurality of signal lines between the second integrated circuit buffer device and the fourth plurality of integrated circuit memory devices.

20. The memory system of claim 18, wherein the first integrated circuit buffer device includes a write buffer to hold data to be provided to at least one integrated circuit memory device of the first plurality of integrated circuit memory devices.

21. The memory system of claim 18, wherein each integrated circuit memory device of the first plurality of integrated circuit memory devices includes a dynamic random access memory cell array.

22. The memory system of claim 18, wherein the first point-to-point link includes a bi-directional link.