Power saving operation of an apparatus with a cache memory

• US 7,523,331 B2
• Filed: 08/30/2004
• Issued: 04/21/2009
• Est. Priority Date: 09/16/2003
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Der Heijden, Gerardus Wilhelmus Theodorus
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Bae, Ji H
• Application Number:
  US10/571,636
• Publication Number:
  US 20070055901A1
• Time in Patent Office: 1,695 Days
• Field of Search: 713/300, 713/320, 713/324, 713/323
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3225 of memory devices

Abstract

An apparatus that contains an instruction processing circuit (14), a main memory (18) addressable by the instruction processing circuit (14) and a cache memory (16). In a normal mode the cache memory (16) is used to cache a part of data and/or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18). The circuit is able to switch to a low power operating mode. Upon the switch an interrupt program for executing a function during operation in the low power operating mode is loaded into the cache memory (16) from the main memory (18). Power supply to the main memory (18) is then switched off, but keeping at least a part of the cache memory (16) continuous to receive power supply. This part ensures that the program of instructions for executing the function is available to the instruction processing circuit. The program is executed from said at least part of the cache memory (16) in the low power operating mode.

Claims

1. An apparatus that is switchable to a low power operating mode and to a normal operating mode, the apparatus comprising:

an instruction processing circuit;

a main memory for providing instructions for the instruction processing circuit during execution by the instruction processing circuit;

a cache memory coupled between the instruction processing circuit and the main memory, operable in the normal operating mode to cache a part of data and/or instructions that the instruction processing circuit addresses in the main memory during execution, and to substitute cached data and/or instructions when the instruction processing circuit addresses the data and/or instructions in the main memory;

low power operating mode activating circuit, arranged to keep part of the apparatus deactivated during operation in the low power operating mode, said part of the apparatus including the main memory, but excluding at least part of the cache memory, the low power mode activating circuit being arranged to load a program of instructions for executing a function during operation in the low power operating mode into said at least part of the cache memory before switching to the low power operating mode;

wherein the instruction processing circuit is configured to;

detect when it is no longer necessary to operate in the normal operating mode;

cause the program of instructions to be loaded into the cache memory when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode; and

signal to a main power supply circuit to deactivate itself when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode, wherein a cache management unit of the cache memory is deactivated in the low power operating mode.

2. An apparatus according to claim 1, wherein the cache memory is switchable to a locked state, wherein the cache memory is disabled from discarding locked information, the low power operating mode activating circuit being arranged to switch the cache memory to the locked state so as to lock the program of instructions for executing the function in the cache memory.

3. An apparatus according to claim 1, wherein the low power operating mode activating circuit is arranged to load, upon switching to the low power operating mode, all data into the cache memory that will be addressed with addresses in main memory by the program of instructions for executing the function.

4. An apparatus according to claim 1, wherein said program of instructions for executing a function in the low power operating mode is an interrupt program, the apparatus comprising an interrupt circuit for triggering the instruction processing circuit to execute the interrupt program at selected times during operation in the low power operating mode.

5. An apparatus that is switchable to a low power operating mode and to a normal operating mode, the apparatus comprising:

an instruction processing circuit;

a main memory for providing instructions for the instruction processing circuit during execution by the instruction processing circuit;

a cache memory coupled between the instruction processing circuit and the main memory, operable in the normal operating mode to cache a part of data and/or instructions that the instruction processing circuit addresses in the main memory during execution, and to substitute cached data and/or instructions when the instruction processing circuit addresses the data and/or instructions in the main memory;

low power operating mode activating circuit, arranged to keep part of the apparatus deactivated during operation in the low power operating mode, said part of the apparatus including the main memory, but excluding at least part of the cache memory, the low power mode activating circuit being arranged to load a program of instructions for executing a function during operation in the low power operating mode into said at least part of the cache memory before switching to the low power operating mode;

wherein the instruction processing circuit is configured to;

detect when it is no longer necessary to operate in the normal operating mode;

cause the program of instructions to be loaded into the cache memory when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode; and

signal to a main power supply circuit to deactivate itself when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode, wherein address comparison circuits of the cache memory are deactivated in the low power operating mode.

6. An apparatus that is switchable to a low power operating mode and to a normal operating mode, the apparatus comprising:

an instruction processing circuit;

a main memory for providing instructions for the instruction processing circuit during execution by the instruction processing circuit;

a cache memory coupled between the instruction processing circuit and the main memory, operable in the normal operating mode to cache a part of data and/or instructions that the instruction processing circuit addresses in the main memory during execution, and to substitute cached data and/or instructions when the instruction processing circuit addresses the data and/or instructions in the main memory;

low power operating mode activating circuit, arranged to keep part of the apparatus deactivated during operation in the low power operating mode, said part of the apparatus including the main memory, but excluding at least part of the cache memory, the low power mode activating circuit being arranged to load a program of instructions for executing a function during operation in the low power operating mode into said at least part of the cache memory before switching to the low power operating mode;

wherein the instruction processing circuit is configured to;

detect when it is no longer necessary to operate in the normal operating mode;

cause the program of instructions to be loaded into the cache memory when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode; and

signal to a main power supply circuit to deactivate itself when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode, wherein excess storage capacity of the cache memory is deactivated in the low power operating mode.

7. A method of operating an apparatus that contains an instruction processing circuit, a main memory addressable by the instruction processing circuit and a cache memory, the method comprising:

using the cache memory and the main memory in a normal operating mode, to cache in cache memory a part of data and/or instructions that the instruction processing circuit addresses in the main memory during execution, and to substitute cached data and/or instructions when the instruction processing circuit addresses the data and/or instructions in the main memory;

storing, in the main memory, a program of instructions for executing an interrupt function during operating in a low power operating mode, wherein the interrupt program is stored at addresses in main memory that have been selected so that all instructions of the interrupt program can be stored together in the cache memory;

detecting that it is no longer necessary to operate in the normal operating mode;

switching to the low power operating mode once it is detected that it is no longer necessary to operate in the normal operating mode, by

loading the interrupt program into the cache memory from the main memory, wherein all instructions of the interrupt program are stored together in the cache memory;

deactivating the main memory to reduce power consumption, but keeping active at least a part of the cache memory, that is needed for retrieving the interrupt program and for executing the interrupt function;

executing the interrupt program from said at least part of the cache memory.

8. The method according to claim 7, wherein switching to the low power operating mode further comprises deactivating a cache management unit of the cache memory.

9. The method according to claim 7, wherein switching to the low power operating mode further comprises deactivating address comparison circuits of the cache memory.

10. The method according to claim 7, wherein switching to the low power operating mode further comprises deactivating excess storage capacity of the cache memory.