Phase shifter with reduced linear dependency
First Claim
Patent Images
1. A method, comprising:
- providing an integrated circuit to be tested, the integrated circuit capable of receiving test patterns;
providing a linear finite state machine (LFSM) having a substantially balanced load; and
generating a linear phase shifter, the linear phase shifter working in combination with the LFSM to send a plurality of test patterns to the integrated circuit to be tested.
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Abstract
A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
167 Citations
21 Claims
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1. A method, comprising:
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providing an integrated circuit to be tested, the integrated circuit capable of receiving test patterns; providing a linear finite state machine (LFSM) having a substantially balanced load; and generating a linear phase shifter, the linear phase shifter working in combination with the LFSM to send a plurality of test patterns to the integrated circuit to be tested. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A linear finite state machine and phase shifter combination, comprising:
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a linear finite state machine including a plurality of memory elements coupled in series; and a phase shifter including a plurality of logic gates coupled to selected memory elements of the linear finite state machine, each of the selected memory elements being coupled to a substantially similar number of logic gates in the phase shifter. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An apparatus comprising:
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means for generating test patterns to test an integrated circuit, the means for generating having a balanced load on its outputs; and means for phase shifting the generated test patterns. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification