Radiation-hardened silicon-on-insulator CMOS device, and method of making the same
First Claim
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1. A method of radiation hardening an ultrathin silicon on sapphire P-channel transistor including the act of:
- implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface.
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Abstract
A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.
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Citations
14 Claims
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1. A method of radiation hardening an ultrathin silicon on sapphire P-channel transistor including the act of:
implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A radiation hardened ultrathin silicon on sapphire P-channel transistor product produced by a process comprising the steps of:
implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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