Post passivation interconnection schemes on top of IC chip

• US 7,524,759 B2
• Filed: 09/17/2007
• Issued: 04/28/2009
• Est. Priority Date: 10/18/2000
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Ghyka; Alexander G
• Application Number:
  US11/856,083
• Publication Number:
  US 20080057703A1
• Time in Patent Office: 589 Days
• Field of Search: 438/622, 438/623, 438/637
• US Class Current: 438/637
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A method for fabricating a chip, comprising:

providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and a passivation layer over said dielectric layer; and

forming a clock bus over said passivation layer, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said clock bus and said second interconnecting structure, and wherein said forming said clock bus comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.

2. The method of claim 1, wherein said forming said first metal layer comprises a sputtering process.

3. The method of claim 1, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process.

4. The method of claim 1, wherein said first and second interconnecting structures are formed by a process comprising a sputtering process and an etching process.

5. The method of claim 1 further comprising forming a polymer layer over said passivation layer, wherein said clock bus is in said polymer layer.

6. The method of claim 5, wherein said polymer layer has a thickness greater than 2 micrometers.

7. The method of claim 1, wherein said clock bus has a thickness greater than 1 micrometer.

8. The method of claim 1, wherein said passivation layer comprises a topmost insulating nitride layer of said chip.

9. The method of claim 1, wherein said passivation layer comprises a nitride layer and an oxide layer.

10. The method of claim 1, wherein said passivation layer comprises a nitride layer.

11. The method of claim 1 further comprising providing a driver, receiver or I/O circuit in or on said silicon substrate, wherein said driver, receiver or I/O circuit has a first terminal connected to said first and second internal circuits through said clock bus.

12. The method of claim 11 further comprising providing an electrostatic discharge (ESD) circuit in or on said silicon substrate, wherein said electrostatic discharge circuit is connected to a second terminal of said driver, receiver or I/O circuit.

13. The method of claim 12 further comprising providing an external connection point connected to said ESD circuit and to said second terminal.