TFT mask ROM and method for making same

• US 7,525,137 B2
• Filed: 07/12/2006
• Issued: 04/28/2009
• Est. Priority Date: 08/13/2001
• Status: Expired due to Term

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Walker, Andrew J., Petti, Christopher
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US11/484,757
• Publication Number:
  US 20060249735A1
• Time in Patent Office: 1,021 Days
• Field of Search: 257/7, 257/74, 257/278, 257/390, 257/E21.614, 257/E21.662, 257/E21.667, 257/E21.671, 257/E21.677, 257/E27.026, 257/E27.103, 257/E33.077
• US Class Current: 257/278
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/383 Channel doping programmed
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM
• CPC Class Codes: H10B 20/60 Peripheral circuit regions
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

Claims

1. A TFT mask ROM array, comprising:

a first plurality of spaced apart conductor rails disposed at a first height above a substrate in a first direction;

a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first direction, each rail stack including;

a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductor rails;

a conductive film; and

a gate insulating film disposed between a second surface of the first semiconductor layer and the conductive film;

wherein TFTs are formed at intersections of two adjacent conductor rails and one rail stack; and

wherein the TFTs comprise a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

2. The array of claim 1, wherein:

the first plurality of rails comprise polysilicon layers of a first conductivity type in contact with metal or a metal silicide layers;

the first semiconductor layer comprises a polysilicon layer;

the gate insulating layer comprises a portion of a charge storage region; and

the conductive film comprises a polysilicon layer and a metal suicide layer.

3. The array of claim 2, wherein:

the polysilicon layers of the first rails comprise at least a portion of the TFT source and drain regions;

the conductive film comprises a gate of the TFTs;

portions of the first semiconductor layer comprise TFT channel regions of a second conductivity type; and

the charge storage region comprises a dielectric isolated floating gate, an ONO dielectric film or an insulating layer containing conductive nanocrystals.

4. The array of claim 3, further comprising:

doped regions of a first conductivity type in the first semiconductor layer comprising portions of the source and drain regions;

a first insulating layer located between the first rails; and

a second insulating layer located between the second rail stacks.

5. The array of claim 2, wherein the first rails are located below the second rail stacks.

6. The array of claim 2, wherein the first rails are located above the second rail stacks.

7. The array of claim 1, wherein the second set of TFTs comprises a set of totally disabled TFTs.

8. The array of claim 1, wherein the second set of TFTs comprises a plurality of totally disabled TFTs and a plurality of partially disabled TFTs.

9. The array of claim 1, wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively removed.

10. The array of claim 1, wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially or totally inoperative.

11. A monolithic three dimensional TFT mask ROM array, comprising a plurality of device levels, each device level comprising the array of claim 1.