Reconfigurable IC that has sections running at different looperness

• US 7,525,342 B2
• Filed: 08/18/2007
• Issued: 04/28/2009
• Est. Priority Date: 11/08/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Redgrave, Jason, Teig, Steven
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/840,963
• Publication Number:
  US 20080036494A1
• Time in Patent Office: 619 Days
• Field of Search: 326 38- 41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration

Abstract

Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit'"'"'s set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.

Claims

1. An integrated circuit (IC) comprising:

a) first and second tiles comprising sets of reconfigurable circuits;

b) first and second sets of configuration data for reconfiguring the sets of reconfigurable circuits of the first and second tiles; and

c) a clock for supplying a clock signal to the first and second tiles, wherein the set of circuits of the first tile receive N number of configuration data sets of the first set of configuration data at a first rate based on the clock signal and the set of circuits of the second tile receive M number of configuration data sets of the second set of configuration data at a second rate based on the clock signal.

2. The IC of claim 1, wherein N and M are different.

3. The IC of claim 1, wherein the first and second tiles have the ability to store the same number of configuration data sets for the particular reconfigurable circuits in the two tiles, but the particular reconfigurable circuit in the first tile iterates through a smaller sub-set of the configuration data sets than the particular reconfigurable circuit in the second tile.

4. The IC of claim 1, wherein the sets of reconfigurable circuits comprise reconfigurable logic circuits each for configurably performing a set of functions, wherein a configuration data set for a reconfigurable logic circuit specifies a function for the reconfigurable logic circuit to perform within the reconfigurable logic circuit'"'"'s set of functions.

5. The IC of claim 4 wherein the sets of reconfigurable circuits further comprise reconfigurable interconnect circuits each for configurably performing a set of interconnect operations, wherein a configuration data set for a reconfigurable interconnect circuit specifies an interconnect operation for the reconfigurable interconnect circuit to perform within the reconfigurable interconnect circuit'"'"'s set of interconnect operations.

6. The IC of claim 5, wherein the reconfigurable interconnect circuits comprise reconfigurable routing circuits for configurably routing signals between the reconfigurable logic circuits.

7. The IC of claim 1, wherein the sets of reconfigurable circuits of the first tile iterate through the N number of configuration data sets at the first rate and the sets of reconfigurable circuits of the second tile iterate through the M number of configuration data sets at the second rate, wherein the first rate is different than the second rate.

8. The IC of claim 1, wherein the first rate is the same as the second rate.

9. The IC of claim 1, wherein the sets of reconfigurable circuits of the first tile reconfigure using a smaller sub-set of the received N number of configuration data sets.

10. The IC of claim 1, wherein the first and second rates are faster than a rate of the clock signal.

11. An electronic device comprising:

an integrated circuit (IC) comprising;

a) first and second tiles comprising sets of reconfigurable circuits;

b) first and second sets of configuration data for reconfiguring the sets of reconfigurable circuits of the first and second tiles; and

c) a clock for supplying a clock signal to the first and second tiles, wherein the set of circuits of the first tile receive N number of configuration data sets of the first set of configuration data at a first rate based on the clock signal and the set of circuits of the second tile receive M number of configuration data sets of the second set of configuration data at a second rate based on the clock signal.

12. The electronic device of claim 11, wherein N and M are different.

13. The electronic device of claim 11, wherein the first and second tiles have the ability to store the same number of configuration data sets for the particular reconfigurable circuits in the two tiles, but the particular reconfigurable circuit in the first section iterates through a smaller sub-set of the configuration data sets than the particular reconfigurable circuit in the second section.

14. The electronic device of claim 11, wherein the sets of reconfigurable circuits comprise reconfigurable logic circuits each for configurably performing a set of functions, wherein a configuration data set for a reconfigurable logic circuit specifies a function for the reconfigurable logic circuit to perform within the reconfigurable logic circuit'"'"'s set of functions.

15. The electronic device of claim 14, wherein the sets of reconfigurable circuits further comprise reconfigurable interconnect circuits each for configurably performing a set of interconnect operations, wherein a configuration data set for a reconfigurable interconnect circuit specifies an interconnect operation for the reconfigurable interconnect circuit to perform within the reconfigurable interconnect circuit'"'"'s set of interconnect operations.

16. The electronic device of claim 15, wherein the reconfigurable interconnect circuits comprise reconfigurable routing circuits for configurably routing signals between the reconfigurable logic circuits.

17. The electronic device of claim 11, wherein the sets of reconfigurable circuits of the first tile iterate through the N number of configuration data sets at the first rate and the sets of reconfigurable circuits of the second tile iterate through the M number of configuration data sets at the second rate, wherein the first rate is different than the second rate.

18. The electronic device of claim 11, wherein the first rate is the same as the second rate.

19. The electronic device of claim 11, wherein the sets of reconfigurable circuits of the first tile reconfigure using a smaller sub-set of the received N number of configuration data sets.

20. The electronic device of claim 11, wherein the first and second rates are faster than a rate of the clock signal.