Please download the dossier by clicking on the dossier button x
×

Circuit for classifying signals

  • US 7,525,349 B2
  • Filed: 08/14/2006
  • Issued: 04/28/2009
  • Est. Priority Date: 08/14/2006
  • Status: Expired due to Fees
First Claim
Patent Images

1. An array of analog circuits for detection of patterns of analog input signals, the array of analog circuits comprising:

  • a plurality of input ports operative to receive a plurality of analog input signals;

    a plurality of circuits, corresponding to the plurality of the input ports, each operative to receive one of the plurality of the analog input signals, the plurality of the circuits being connected to at least an address bus for selecting one of the plurality of the circuits, an analog bus for delivering the plurality of the analog input signals to a signal processor, and a spike bus for delivering the indications provided by each of the output modules of the plurality of the circuits to the signal processor, each circuit comprising;

    a first analog memory component operative to store a threshold value;

    a threshold detection module operative to determine whether the analog input signal exceeds the threshold value;

    a time delay module operative to delay a processing of the one of the analog input signals by an amount equal to a corresponding window time delay;

    an amplitude window calculation module operative to determine, after a lapse of the corresponding window time delay, whether an amplitude of the one of the analog input signals is between a corresponding lower limit and a corresponding upper limit of a corresponding amplitude window; and

    an output module providing an indication of whether the amplitude of the one of the analog input signals is between the corresponding lower and the corresponding upper limit of the corresponding amplitude window, wherein the indication is used to determine whether the one of the analog input signals belongs to at least one of a plurality of pre-determined classes of analog signals; and

    an array control module operative to select one of the plurality of the circuits, the array control module comprising an address decoder for selecting one of the plurality of the circuits using at least one of the address bus, the analog bus, and the spike bus.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×