System and method for modeling LPAR behaviors in a simulation tool

• US 7,526,421 B2
• Filed: 02/27/2004
• Issued: 04/28/2009
• Est. Priority Date: 02/27/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Deitch, Martin
• Primary Examiner(s): Shah; Kamini S
• Assistant Examiner(s): PATEL, SHAMBHAVI K
• Application Number:
  US10/789,262
• Publication Number:
  US 20050192781A1
• Time in Patent Office: 1,887 Days
• Field of Search: 703/21, 710/36, 710/8, 710/5, 713/1, 709/226, 718/104
• US Class Current: 703/21
• CPC Class Codes: G06F 11/3442 for planning or managing the needed capacity
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation
• CPC Class Codes: G06F 2201/86 Event-based monitoring

Abstract

A simulation tool for modeling LPAR behavior in a mainframe computer. The simulation tool comprises: a first algorithm for modeling the behavior of an LPAR (logical partition) operating in a time slice dispatch mode; and a second algorithm for modeling the behavior of a plurality of LPARs.

Claims

1. A method for modeling a behavior of an LPAR (logical partition) in a simulated computer operating in a time slice dispatch mode, comprising:

beginning a modeling interval;

calculating a resource percentage representing a percentage of total resources allocated to the LPAR, wherein the resource percentage is equal to;

100%−

a percentage of resources allocated to all other LPARs running in the simulated computer;

calculating a time slice percentage for the LPAR based on the resource percentage and CP (central processor) data, wherein;

$\mathrm{time}<br><br><br><br>\mathrm{slice}<br><br><br><br>\mathrm{percentage}=\frac{\left(\mathrm{resource}<br><br><br><br>\mathrm{percentage}\right)\times <br><br>\left(\#<br><br><br><br>\mathrm{of}<br><br><br><br>\mathrm{physical}<br><br><br><br>\mathrm{CPs}\right)}{\left(\#<br><br><br><br>\mathrm{of}<br><br><br><br>\mathrm{logical}<br><br><br><br>\mathrm{CPs}\right)};<br><br>$

determining a CP (central processor) percentage representing a percentage of time that all physical CPs in the computer being modeled have been allocated to the LPAR;

if the CP percentage is greater than the time slice percentage, causing the simulated computer not to dispatch CPs to the LPAR; and

outputting and displaying the behavior of the modeling.

2. The method of claim 1, including the further step of repeating each of the recited steps for a next modeling interval.

3. The method of claim 1, wherein the percentage of resources allocated to all other LPARs is based on a weighting factor specified for each LPAR, a number of logical CPs allocated to each LPAR, and a MIPs (million instructions per second) value for each LPAR.

4. The method of claim 3, wherein the MIPs value represents a maximum consumption that each LPAR could consume in an unrestrained processor.