Packet combiner for a packetized bus with dynamic holdoff time
First Claim
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1. A bus interface device for transmitting data transfer requests from a plurality of clients as packets on a bus, the device comprising:
- a queue configured to store a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range;
control logic configured to generate a send condition signal;
packet forming logic configured to form a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic being further configured to combine two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable, wherein the data transfer requests are write requests;
output logic coupled to the packet forming logic and configured to drive the packet onto the bus; and
dynamic holdoff timer logic coupled to the packet forming logic and the control logic and configured to determine a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period, the dynamic holdoff timer logic being further configured to receive size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information, the size information representing an amount of write data included in the formed packetthe control logic being configured to generate the send condition signal in response to expiration of the holdoff period.
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Abstract
Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.
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Citations
20 Claims
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1. A bus interface device for transmitting data transfer requests from a plurality of clients as packets on a bus, the device comprising:
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a queue configured to store a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range; control logic configured to generate a send condition signal; packet forming logic configured to form a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic being further configured to combine two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable, wherein the data transfer requests are write requests; output logic coupled to the packet forming logic and configured to drive the packet onto the bus; and dynamic holdoff timer logic coupled to the packet forming logic and the control logic and configured to determine a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period, the dynamic holdoff timer logic being further configured to receive size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information, the size information representing an amount of write data included in the formed packet the control logic being configured to generate the send condition signal in response to expiration of the holdoff period. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for transmitting data transfer requests from a plurality of clients as packets on a bus, the method comprising:
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receiving a first data transfer request specifying a first address range; detecting whether a holdoff time has elapsed since receiving the first packet, wherein the holdoff time is dynamically adjustable; in the event that the holdoff time has elapsed, forming a packet for transmission on the bus, wherein forming the packet includes; determining whether a subsequent data transfer request specifying a second address range mergeable with the first address range was received during the holdoff time; in the event that a subsequent data transfer request specifying a mergeable second address range was received, merging the first data transfer request and the mergeable subsequent data transfer request into the packet, and in the event that no subsequent data transfer request specifying a mergeable second address range was received during the holdoff time, including only the first data transfer request in the packet; transmitting the packet onto the bus; and adjusting, based on a level of bus activity, the holdoff time for a next packet to be formed, wherein adjusting the holdoff time includes; determining a delay time associated with the data transfer request; and adding the delay time to a current holdoff time, thereby adjusting the holdoff time. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A processor comprising:
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a plurality of processing cores, each processing core configured to generate data transfer requests; and a bus interface unit configured to receive data transfer requests from the processing cores and to transmit the data transfer requests as packets on a bus, the bus interface unit including; a queue configured to store a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range; control logic configured to generate a send condition signal; packet forming logic configured to form a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic being further configured to combine two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable, wherein the data transfer requests are write requests; output logic coupled to the packet forming logic and configured to drive the packet onto the bus; and dynamic holdoff timer logic coupled to the packet forming logic and the control logic and configured to determine a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period, the dynamic holdoff timer logic being further configured to receive size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information, the size information representing an amount of write data included in the formed packet, the control logic being configured to generate the send condition signal in response to expiration of the holdoff period. - View Dependent Claims (15, 16, 17, 18)
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19. A bus interface device for transmitting data transfer requests from a plurality of clients as packets on a bias, the device comprising:
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a queue for storing a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range, wherein the data transfer requests are read requests; control logic for generating a send condition signal; packet forming logic for forming a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic also combines two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable; output logic coupled to the packet forming logic for driving the packet onto the bus; and dynamic holdoff timer logic coupled to the packet forming logic and the control logic, the dynamic holdoff time logic for determining a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period, wherein the dynamic holdoff timer logic is also receives size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information, the size information representing an amount of data requested by the formed packet, the control logic also generates the send condition signal in response to expiration of the holdoff period.
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20. A processor comprising:
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a plurality of processing cores, each processing core for generating data transfer requests; and a bus interface unit for receiving data transfer requests from the processing cores and to transmit the data transfer requests as packets on a bus, the bus interface unit including; a queue storing a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range, wherein the data transfer requests are read requests; control logic for generating a send condition signal; packet forming logic for forming a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic also combines two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable; output logic coupled to the packet forming logic for driving the packet onto the bus; and dynamic holdoff timer logic coupled to the packet forming logic and the control logic, the dynamic holdoff timer logic for determining a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period, wherein the dynamic holdoff timer logic also receives size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information, the size information representing an amount of data requested by the formed packet, the control logic being configured to generate the send condition signal in response to expiration of the holdoff period.
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Specification