Buffered memory having a control bus and dedicated data lines

• US 7,526,597 B2
• Filed: 10/05/2007
• Issued: 04/28/2009
• Est. Priority Date: 01/05/2000
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard, Tsern, Ely, Ware, Fred
• Primary Examiner(s): Verbrugge; Kevin
• Application Number:
  US11/868,242
• Publication Number:
  US 20080034130A1
• Time in Patent Office: 571 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H05K 1/181 associated with surface mounted components

Abstract

A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

Claims

1. A circuit board comprising:

a bus to transport control information; and

a plurality of memory subsystems, coupled to the bus, wherein each memory subsystem of the plurality of memory subsystems includes;

an integrated circuit buffer device comprising;

a port to receive the control information from the bus; and

a point-to-point link port to receive data, wherein the point-to-point link port includes a configurable width; and

a plurality of integrated circuit memory devices to receive the data and control information from the integrated circuit buffer device and store the data in response to the control information.

2. The circuit board of claim 1, wherein the plurality of integrated circuit memory devices includes flash memory devices.

3. The circuit board of claim 1, wherein each integrated circuit memory device of the plurality of integrated circuit memory devices is a double data rate synchronous dynamic random access memory device.

4. The circuit board of claim 1, wherein the plurality of integrated circuit memory devices is stacked on top of the integrated circuit buffer device.

5. The circuit board of claim 4, further comprising:

flexible tape interconnect that interconnects the plurality of integrated circuit memory devices and the integrated circuit buffer device.

6. The circuit board of claim 1, further comprising a plurality of bidirectional point-to-point links coupled to the plurality of memory subsystems, wherein each memory subsystem of the plurality of memory subsystems includes a corresponding bidirectional point-to-point link of the plurality of bidirectional point-to-point links connected to the point-to-point link port of the integrated circuit buffer device.

7. The circuit board of claim 6, further comprising an integrated circuit controller connected to the bus and each bidirectional point-to-point link of the plurality of bidirectional point-to-point links, the integrated circuit controller to provide the control information to the bus and the data to the plurality of bidirectional point-to-point links.

8. The circuit board of claim 7, further comprising:

the integrated circuit controller to provide address information to the bus, wherein the address information specifies where to store the data in the plurality of integrated circuit memory devices.

9. The circuit board of claim 1, wherein the control information is transported on the bus using a first protocol, wherein the integrated circuit buffer device translates the control information such that the control information is provided to the plurality of integrated circuit memory devices using a second protocol.

10. A system comprising:

an integrated circuit controller device to generate control information;

a bus, coupled to the integrated circuit controller device, to transport the control information;

a first integrated circuit buffer device coupled to the bus, the first integrated circuit buffer device to receive the control information from the bus, the first integrated circuit buffer device includes a configurable width interface;

a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device, wherein, in response to the control information, first data is transferred between the first plurality of integrated circuit memory devices and the first integrated circuit buffer device;

a first point-to-point link coupled to the first integrated circuit buffer device and the integrated circuit controller device, the first point-to-point link to transport the first data between the first integrated circuit buffer device and the integrated circuit controller device;

a second integrated circuit buffer device coupled to the bus, the second integrated circuit buffer device to receive the control information from the bus;

a second plurality of integrated circuit memory devices coupled to the second integrated circuit buffer device, wherein, in response to the control information, second data is transferred between the second plurality of integrated circuit memory devices and the second integrated circuit buffer device; and

a second point-to-point link coupled to the second integrated circuit buffer device and the integrated circuit controller device, the second point-to-point link to transport the second data between the second integrated circuit buffer device and the integrated circuit controller device.

11. The system of claim 10, wherein:

the first point-to-point link includes a first plurality of signal lines, wherein the transporting of the first data between the first integrated circuit buffer device and the integrated circuit controller device is bidirectional over the first plurality of signal lines; and

the second point-to-point link includes a second plurality of signal lines, wherein the transporting of the second data between the second integrated circuit buffer device and the integrated circuit controller device is bidirectional over the second plurality of signal lines.

12. The system of claim 11, wherein:

bandwidth of the first data transported over the first plurality of signal lines matches bandwidth of the first data transferred between the first plurality of integrated circuit memory devices and the first integrated circuit buffer device; and

bandwidth of the second data transported over the second plurality of signal lines matches bandwidth of the second data transferred between the second plurality of integrated circuit memory devices and the second integrated circuit buffer device.

13. The system of claim 10, wherein:

the first plurality of integrated circuit memory devices and the first integrated circuit buffer device are included on a first memory module; and

the second plurality of integrated circuit memory devices and the second integrated circuit buffer device are included on a second memory module.

14. The system of claim 10, wherein the first integrated circuit buffer device, second integrated circuit buffer device, first plurality of integrated circuit memory devices, and second plurality of integrated circuit memory devices are all disposed on a common circuit board substrate.

15. The system of claim 14, wherein the integrated circuit controller device is disposed on the common circuit board substrate.

16. A system comprising:

an integrated circuit controller device having a plurality of ports;

a bus coupled to the integrated circuit controller device, the bus to transport control information generated by the integrated circuit controller device; and

a plurality of memory subsystems, coupled to the bus, to receive the control information, wherein each memory subsystem of the plurality of memory subsystems includes;

a plurality of integrated circuit memory devices configured to output data; and

an integrated circuit buffer device including;

a first port to receive the control information from the bus;

a second port to provide the control information to the plurality of integrated circuit memory devices, wherein the plurality of integrated circuit memory devices are configured to output the data in response to the control information;

a third port to receive the data from the plurality of integrated circuit memory devices; and

a fourth port to output the data to a corresponding port of the plurality of ports included on the integrated circuit controller device, wherein the fourth port of the integrated circuit buffer device includes a configurable width.

17. The system of claim 16, wherein the plurality of memory subsystems and the integrated circuit controller device are disposed on a circuit board substrate.

18. The system of claim 16, further including a plurality of circuit board substrates, wherein each memory subsystem of the plurality of memory subsystems is disposed on a corresponding circuit board substrate of the plurality of circuit board substrates.

19. The system of claim 16, wherein each integrated circuit buffer device includes a multiplexer, coupled to the third port, to receive the data from the plurality of integrated circuit memory devices and to provide, as output on the fourth port, the data in a serialized format.

20. The system of claim 16, wherein each memory subsystem of the plurality of memory subsystems further comprises a plurality of channels to transport the data between the plurality of integrated circuit memory devices and the integrated circuit buffer device, wherein address information transmitted from the integrated circuit controller device to the first port of the buffer device via the bus is used to determine subsets of channels of the plurality of channels used to transport the data between the plurality of integrated circuit memory devices and the integrated circuit buffer device.

21. A system comprising:

an integrated circuit controller device;

a bus coupled to the integrated circuit controller device, the bus to transport control information generated by the integrated circuit controller device; and

a plurality of integrated circuit buffer devices, coupled to the bus, to receive the control information from the bus, wherein each integrated circuit buffer device of the plurality of integrated circuit buffer devices includes;

a first port to receive data output from the integrated circuit controller device, wherein the first port of the integrated circuit buffer device is included in a configurable width interface;

a second port to provide the control information and a first portion of the data to a first plurality of memory devices; and

a third port to provide the control information and a second portion of the data to a second plurality of memory devices.

22. A circuit board comprising:

a plurality of memory subsystems, coupled to a bus, to receive control information from the bus, wherein each memory subsystem of the plurality of memory subsystems includes;

an integrated circuit buffer device to receive the control information from the bus, wherein the integrated circuit buffer device includes a configurable width to transfer data;

a first integrated circuit memory device;

a second integrated circuit memory device;

a first plurality of signal lines coupled to the first integrated circuit memory device and the integrated circuit buffer device, the first plurality of signal lines to transport first data between the first integrated circuit memory device and the integrated circuit buffer device;

a first set of control lines coupled to the first integrated circuit memory device and the integrated circuit buffer device, the first set of control lines to provide the control information received by the integrated circuit buffer device to the first integrated circuit memory device;

a second plurality of signal lines coupled to the second integrated circuit memory device and the integrated circuit buffer device, the second plurality of signal lines to transport second data between the second integrated circuit memory device and the integrated circuit buffer device; and

a second set of control lines coupled to the second integrated circuit memory device and the integrated circuit buffer device, the second set of control lines to provide the control information received by the integrated circuit buffer device to the second integrated circuit memory device.

23. The circuit board of claim 22, further comprising a plurality of point-to-point links to transport data, each link of the plurality of point-to-point links having:

a first end connected to an integrated circuit controller; and

a second end connected to a corresponding integrated circuit buffer device included in each memory subsystem of the plurality of memory subsystems.

24. The circuit board of claim 22, wherein each of the first integrated circuit memory device and the second integrated circuit memory device includes dynamic random access memory cells.