Vector processing apparatus with overtaking function to change instruction execution order

• US 7,526,629 B2
• Filed: 02/23/2005
• Issued: 04/28/2009
• Est. Priority Date: 02/23/2004
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Saida, Yasumasa
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): LINDLOF, JOHN M
• Application Number:
  US11/062,561
• Publication Number:
  US 20050188178A1
• Time in Patent Office: 1,525 Days
• Field of Search: 712/2
• US Class Current: 712/2
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution

Abstract

A vector processing apparatus includes a main memory, an instruction issuing section which issues instructions, an overtaking control circuit which outputs the instructions received from the instruction issuing section to an instruction executing section in an order based on whether each of a first and second instructions belongs to a first specific instruction group, whether each of the first and second instructions belongs to a second specific instruction group in the first specific instruction group, whether a fourth instruction belongs to a fourth specific instruction group, whether a third instruction belongs to a third specific instruction group, and whether an address area of the main memory relating to the third instruction and an address area of the main memory relating to each of the first and second instructions do not overlap, and the instruction executing section executes the instructions received from the overtaking control circuit.

Claims

1. A vector processing apparatus comprising:

a main memory;

an instruction issuing section configured to sequentially issue instructions, which contain instructions associated with access to said main memory;

an overtaking control circuit, which performs overtaking control, configured to output said instructions received from said instruction issuing section to an instruction executing section in an order determined based on whether there are instructions belonging to a first specific instruction group before a last instruction, whether there are instructions belonging to a second specific instruction group in said first specific instruction group before said last instruction, whether there are instructions belonging to a third specific instruction group before said last instruction, whether said last instruction belongs to a fourth specific instruction group, and whether an address area of said main memory relating to said last instruction and an address area of said main memory relating to each of said instructions belonging to said second specific instruction group do not overlap at all,

wherein the instruction executing section is configured to execute said instructions received from said overtaking control circuit in an order of reception,

wherein the instructions belonging to the second specific instruction group are of a second type, the instructions belonging to the third specific instruction group are of a third type, and instructions belonging to the fourth specific instruction group are of a fourth type,

wherein the second type, the third type, and the fourth type are different from each other,

wherein the overtaking control circuit performs the overtaking control when an address region accessed by a vector store instruction preceding the last instruction does not overlap an address region accessed by the last instruction,

wherein the last instruction is a vector load instruction,

wherein the overtaking control circuit performs the overtaking control by outputting the vector load instruction to the instruction executing section before outputting the vector store instruction to the instruction executing section when the address region accessed by the vector store instruction does not overlap the address region accessed by the vector load instruction.

2. The vector processing apparatus according to claim 1, wherein said overtaking control circuit comprises:

a first decoder configured to detect ones of said received instructions, which belong to said first specific instruction group but does not belong to said second specific instruction group;

a second decoder configured to detect ones of said received instructions, which belong to said second specific instruction group;

a third decoder configured to detect ones of said received instruction, which belong to said third specific instruction group; and

a fourth decoder configured to detect ones of said received instructions which belong to said fourth specific instruction group.

3. The vector processing apparatus according to claim 2, wherein said overtaking control circuit further comprises:

an order holding section configured to hold an order of reception of said received instructions; and

an overtaking determining section configured to determine whether an address area of said main memory relating to said instruction decoded by said fourth decoder and an address area of said main memory relating to said instruction decoded by said second decoder do not overlap at all.

4. The vector processing apparatus according to claim 3, wherein when a first instruction is received and then a second instruction is received in order after said first instruction, said third decoder does not detect any third instruction belonging to said third specific instruction group from said received instructions, and said fourth decoder detects said last instruction as a fourth instruction after said second instruction, said overtaking control circuit outputs said fourth instruction before said first or second instruction, depending on whether each of said first and second instructions belongs to said first specific instruction group, whether each of said first and second instructions belongs to said second specific instruction group, and whether the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to each of said first and second instructions do not overlap at all.

5. The vector processing apparatus according to claim 4, wherein said overtaking control circuit outputs said fourth instruction before said first and second instructions while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said first and second instructions.

6. The vector processing apparatus according to claim 4, wherein said overtaking control circuit outputs said fourth instruction before said first and second instructions while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said first instruction, and said second decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said second instruction do not overlap at all, and

said overtaking control circuit outputs said fourth instruction after said second instruction while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said first instruction, and said second decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said second instruction overlap partially or entirely.

7. The vector processing apparatus according to claim 4, wherein said overtaking control circuit outputs said fourth instruction before said first and second instructions while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said second instruction, and said second decoder detects said first instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said first instruction do not overlap at all, and

said overtaking control circuit outputs said fourth instruction after said first instruction and before said second instruction while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said second instruction, and said second decoder detects said first instruction, and when the address area of said main memory relating to said fourth instruction and an address area of said main memory relating to said first instruction overlap partially or entirely.

8. The vector processing apparatus according to claim 3, wherein when a first instruction is received and then a second instruction is received in order after said first instruction, said third decoder detects a third instruction from said received instructions after said first instruction and before said second instruction, said fourth decoder detects said last instruction as a fourth instruction from said received instructions after said second instruction, said overtaking control circuit outputs said fourth instruction after said third instruction, depending on whether said second instruction belongs to said first specific instruction group, whether said second instruction belongs to said second specific instruction group, and whether the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said second instruction do not overlap at all.

9. The vector processing apparatus according to claim 8, wherein said overtaking control circuit outputs said fourth instruction after said third instruction and before said second instruction while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said second instruction.

10. The vector processing apparatus according to claim 8, wherein said overtaking control circuit outputs said fourth instruction after said third instruction and before said second instruction while keeping the order of said received instructions other than said fourth instruction, when said second decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said second instruction do not overlap at all, and

said overtaking control circuit outputs said fourth instruction after said second instruction while keeping the order of said received instructions other than said fourth instruction, when said second decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said second instruction overlap partially or entirely.

11. The vector processing apparatus according to claim 3, wherein when a first instruction is received and then a second instruction is received in order after said first instruction, said third decoder detects a third instruction from said received instructions before said first instruction, and said fourth decoder detects said last instruction as a fourth instruction from said received instructions, said overtaking control circuit outputs said fourth instruction after said third instruction and before said first or second instruction, depending on whether said first decoder detects each of said first and second instructions, whether said second decoder detects each of said first and second instructions, and whether the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to each of said first and second instructions do not overlap at all.

12. The vector processing apparatus according to claim 11, wherein said overtaking control circuit outputs said fourth instruction after said third instruction and before said first instruction while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said first and second instructions.

13. The vector processing apparatus according to claim 11, wherein said overtaking control circuit outputs said fourth instruction after said third instruction and before said first and second instructions while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said first instruction, and said second decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and an address area of said main memory relating to said second instruction do not overlap at all, and

said overtaking control circuit outputs said fourth instruction after said second instruction while keeping the order of said received instructions other than said fourth instruction, when said first decoder detects said first instruction, and said second decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said second instruction overlap partially or entirely.

14. The vector processing apparatus according to claim 11, wherein said overtaking control circuit outputs said fourth instruction after said third instruction and before said first instruction while keeping the order of said received instructions other than said fourth instruction, when said second decoder detects said first instruction, and said first decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and the address area of said main memory relating to said first instruction do not overlap at all, and

said overtaking control circuit outputs said fourth instruction after said first instruction and before said second instruction while keeping the order of said received instructions other than said fourth instruction, when said second decoder detects said first instruction, and said first decoder detects said second instruction, and when the address area of said main memory relating to said fourth instruction and an address area of said main memory relating to said first instruction overlap partially or entirely.

15. The vector processing apparatus according to claim 1, wherein said first specific instruction group contains a vector gather instruction and the vector store instruction, said second specific instruction group contains the vector store instruction, said third specific instruction group contains a vector scatter instruction, and said fourth specific instruction group contains the vector load instruction.

16. The vector processing apparatus according to claim 15, wherein said fourth specific instruction group contains a scalar load instruction and a scalar store instruction.

17. The vector processing apparatus according to claim 1, wherein the overtaking control circuit performs the overtaking control when an instruction preceding the last instruction is not a vector scatter instruction.