Programmable processor and system for store multiplex operation
First Claim
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1. A programmable processor comprising:
- an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit, the execution unit is operable to;
(i) detect some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and
(ii) cause the write-enabled data bits to be written to a specified memory location.
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Abstract
A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.
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Citations
28 Claims
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1. A programmable processor comprising:
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an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit, the execution unit is operable to; (i) detect some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and (ii) cause the write-enabled data bits to be written to a specified memory location. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing system comprising:
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(a) a bus coupling components in the data processing system; (b) an external memory coupled to the bus; (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising; an instruction path;
a data path;an external interface operable to receive data from an external source and communicate the received data over the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit, the execution unit is operable to; (i) detect some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and (ii) cause the write-enabled data bits to be written to a specified memory location. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A programmable processor comprising:
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a virtual memory addressing unit; an instruction path and a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file comprising a plurality of registers coupled to the data path; and
an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path, the execution unit capable of performing a bitwise insert operation that operates on a first and a second operand stored in at least one register in the register file, the second operand consisting of N independently selectable bits, N being an integer multiple of eight, wherein each bit in the second operand is independently selectable as either having a first predetermined value or a second predetermined value, wherein for each bit in the first operand, the bitwise insert operation inserts the bit into a corresponding bit position in a destination value if a corresponding bit in the second operand has the first predetermined value. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A device having installed therein a programmable processor, the programmable processor comprising:
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a virtual memory addressing unit; an instruction path and a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file comprising a plurality of registers coupled to the data path; and
an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path, the execution unit capable of performing a bitwise insert operation that operates on a first and a second operand stored in at least one register in the register file, the second operand consisting of N independently selectable bits, N being an integer multiple of eight, wherein each bit in the second operand is independently selectable as either having a first predetermined value or a second predetermined value, wherein for each bit in the first operand, the bitwise insert operation inserts the bit into a corresponding bit position in a destination value if a corresponding bit in the second operand has the first predetermined value. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification