Programmable processor and system for store multiplex operation

• US 7,526,635 B2
• Filed: 01/15/2004
• Issued: 04/28/2009
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/757,516
• Publication Number:
  US 20040210746A1
• Time in Patent Office: 1,930 Days
• Field of Search: 712/222, 712/224, 712/220
• US Class Current: 712/224
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.

Claims

1. A programmable processor comprising:

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit, the execution unit is operable to;

(i) detect some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and

(ii) cause the write-enabled data bits to be written to a specified memory location.

2. The processor of claim 1 wherein the execution unit is operable to cause the write-enabled data bits to be written to the specified memory location by reading an unaltered field of data from the specified memory location and writing the unaltered field of data along with the write-enabled data bits to the specified memory location.

3. The processor of claim 1 wherein the mask is contained in a specified register.

4. The processor of claim 1 wherein the memory location is specified by a register.

5. The processor of claim 1 wherein the specified memory location comprises a section of memory having a specific width and beginning at a specific memory address.

6. The processor of claim 1 wherein each write-enabled mask bit is indicated as a logic 1.

7. The processor of claim 1 wherein the execution unit is further operable to, in response to decoding a second single instruction specifying a register containing a first plurality of floating-point operands and another register containing a second plurality of floating-point operands, multiply the first plurality of floating-point operands by the second plurality of floating-point operands to produce a plurality of products and provide the plurality of products to partitioned fields of a result register as a catenated result.

8. A data processing system comprising:

(a) a bus coupling components in the data processing system;

(b) an external memory coupled to the bus;

(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising;

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit, the execution unit is operable to;

(i) detect some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and

(ii) cause the write-enabled data bits to be written to a specified memory location.

9. The system of claim 8 wherein the execution unit is operable to cause the write-enabled data bits to be written to the specified memory location by reading an unaltered field of data from the specified memory location and writing the unaltered field of data along with the write-enabled data bits to the specified memory location.

10. The system of claim 8 wherein the mask is contained in a specified register.

11. The system of claim 8 wherein the memory location is specified by a register.

12. The system of claim 8 wherein the specified memory location comprises a section of memory having a specific width and beginning at a specific memory address.

13. The system of claim 8 wherein each write-enabled mask mask bit is indicated as a logic 1.

14. The system of claim 8 wherein the execution unit is further operable to, in response to decoding a second single instruction specifying a register containing a first plurality of floating-point operands and another register containing a second plurality of floating-point operands, multiply the first plurality of floating-point operands by the second plurality of floating-point operands to produce a plurality of products and provide the plurality of products to partitioned fields of a result register as a catenated result.

15. A programmable processor comprising:

a virtual memory addressing unit;

an instruction path and a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file comprising a plurality of registers coupled to the data path; and

an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path, the execution unit capable of performing a bitwise insert operation that operates on a first and a second operand stored in at least one register in the register file, the second operand consisting of N independently selectable bits, N being an integer multiple of eight, wherein each bit in the second operand is independently selectable as either having a first predetermined value or a second predetermined value, wherein for each bit in the first operand, the bitwise insert operation inserts the bit into a corresponding bit position in a destination value if a corresponding bit in the second operand has the first predetermined value.

16. The programmable processor of claim 15 wherein the first predetermined value is a logic 1.

17. The programmable processor of claim 15 wherein for each bit in the first operand, the bitwise insert operation maintains a corresponding bit position in the destination value as unchanged if a corresponding bit in the second operand has the second predetermined value.

18. The programmable processor of claim 17 wherein the second predetermined value is a logic 0.

19. The programmable processor of claim 15 wherein the bitwise insert operation stores the destination value into memory.

20. The programmable processor of claim 15 wherein each of the first and second operands has a width of 64 bits.

21. The programmable processor of claim 15 wherein the execution unit is further capable of executing a plurality of different group floating-point arithmetic operations that arithmetically operate on multiple floating-point operands stored in partitioned fields of registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual floating-point results.

22. A device having installed therein a programmable processor, the programmable processor comprising:

a virtual memory addressing unit;

an instruction path and a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file comprising a plurality of registers coupled to the data path; and

an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path, the execution unit capable of performing a bitwise insert operation that operates on a first and a second operand stored in at least one register in the register file, the second operand consisting of N independently selectable bits, N being an integer multiple of eight, wherein each bit in the second operand is independently selectable as either having a first predetermined value or a second predetermined value, wherein for each bit in the first operand, the bitwise insert operation inserts the bit into a corresponding bit position in a destination value if a corresponding bit in the second operand has the first predetermined value.

23. The device of claim 22 wherein the first predetermined value is a logic 1.

24. The device of claim 22 wherein for each bit in the first operand, the bitwise insert operation maintains a corresponding bit position in the destination value as unchanged if a corresponding bit in the second operand has the second predetermined value.

25. The device of claim 24 wherein the second predetermined value is a logic 0.

26. The device of claim 22 wherein the bitwise insert operation stores the destination value into memory.

27. The device of claim 22 wherein each of the first and second operands has a width of 64 bits.

28. The device of claim 22 wherein the execution unit is further capable of executing a plurality of different group floating-point arithmetic operations that arithmetically operate on multiple floating-point operands stored in partitioned fields of registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual floating-point results.