Performance state-based thread management

• US 7,526,661 B2
• Filed: 12/02/2004
• Issued: 04/28/2009
• Est. Priority Date: 12/02/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Bodas, Devadatta V., Nakajima, Jun
• Primary Examiner(s): Cao; Chun
• Application Number:
  US11/003,561
• Publication Number:
  US 20060123251A1
• Time in Patent Office: 1,608 Days
• Field of Search: 713/300, 713/320
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods of managing threads provide for selecting a thread for execution and identifying a target performance state of a processor core based on the thread. Identifying the target performance state may include applying a priority of the thread to a mapping policy to obtain the target performance state. In one embodiment, a transition of the selected core to the target performance state can be initiated and the thread can be scheduled for execution by the processor core.

Claims

1. A method comprising:

selecting a thread for execution;

identifying a target performance state based on the thread;

selecting a processor core from a plurality of processor cores;

initiating a transition of the processor core to the target performance state if the processor core is not in the target performance state and none of the remaining cores in the plurality of cores shares a performance state-dependent resource and has a second target performance state that is shallower than the target performance state; and

scheduling the thread for execution by the processor core.

2. The method of claim 1, wherein the identifying includes applying a priority of the thread to a mapping policy to obtain the target performance state.

3. The method of claim 2, further including modifying the mapping policy based on a number of threads in a thread run queue.

4. The method of claim 3, wherein the modifying includes increasing a performance characteristic of the mapping policy if the number of threads is above a threshold.

5. The method of claim 3, wherein the modifying includes increasing a power saving characteristic of the mapping policy if the number of threads is below a threshold.

6. The method of claim 1, wherein the identifying includes identifying an Advanced Configuration and Power Interface (ACPI) P-state.

7. The method of claim 1, wherein the selecting includes searching a thread run queue for a thread having a highest priority.

8. An apparatus comprising:

a processor core within a plurality of processor cores;

scheduling logic to select a thread for execution and identify a target performance state based on the thread, and to schedule the thread for execution by the processor core; and

a performance state controller, the scheduling logic to send a signal to the controller to initiate a transition of the processor core to the target performance state if the processor core is not in the target performance state and none of the remaining cores in the plurality of cores shares a performance state-dependent resource and has a second target performance state that is shallower than the target performance state.

9. The apparatus of claim 8, wherein the scheduling logic is to apply a priority of the thread to a mapping policy to obtain the target performance state.

10. The apparatus of claim 9, wherein the scheduling logic is to modify the mapping policy based on a number of threads in a thread run queue.

11. The apparatus of claim 10, wherein the scheduling logic is to increase a performance characteristic of the mapping policy if the number of threads is above a threshold.

12. The apparatus of claim 10, wherein the scheduling logic is to increase a power saving characteristic of the mapping policy if the number of threads is below a threshold.

13. The apparatus of claim 8, wherein the scheduling logic is to identify an Advanced Configuration and Power Interface (ACPI) P-state.

14. The apparatus of claim 8, further including a thread run queue, the scheduling logic to search the thread queue for a thread having a highest priority.

15. A system comprsing:

a random access memory to store instructions;

a chipset coupled to the random access memory;

a processor, within a plurality of processor cores, coupled to the chipset, the processor having a core and scheduling logic to select a subset of the instructions as a thread for execution and identify a target performance state based on the thread and schedule the thread for execution by the processor core; and

a performance state controller, the scheduling logic to send a signal to the controller to initiate a transition a transition of the processor core to the target performance state if the processor core is not in the target performance state and none of the remaining cores in the plurality of cores shares a performance state-dependent resource and has a second target performance state that is shallower than the target performance state.

16. A method comprising:

searching a thread run queue for a thread having a highest priority;

applying the priority of the thread to a mapping policy to obtain a target Advanced Configuration and Power Interface (ACPI) P-state;

selecting a processor core from a plurality of processor cores;

initiating a transition of the processor core to the P-state if the processor core is not in the P-state and none of the remaining cores in the plurality of cores shares a P-state-dependent resource with the processor core and has a second target P-state that is shallower than the target P-state; and

scheduling the thread for execution by the processor core is in the P-state.

17. The method of claim 16, further including modifying the mapping policy based on a number of threads in the thread run queue.

18. The method of claim 17, wherein the modifying includes increasing a performance characteristic of the mapping policy if the number of threads is above a threshold.

19. The method of claim 17, wherein the modifying includes decreasing a performance characteristic of the mapping policy if the number of threads is below a threshold.

20. A computer readable medium comprising a stored set of instructions which if executed are operable to:

select a thread for execution;

identify a target performance state based on the thread;

select a processor core from a plurality of processor cores;

initiate a transition of the processor to the target performance state if the processor core is not in the target performance state and none of the remaining cores in the plurality or cores shares a performance state-dependent resource and has a second target performance state that is shallower than the target performance state; and

schedule the thread for execution by the processor core.