Drift tracking feedback for communication channels

• US 7,526,664 B2
• Filed: 11/15/2006
• Issued: 04/28/2009
• Est. Priority Date: 03/17/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C., Lambrecht, Frank, Abhyankar, Abhijit M., Chang, Kun Yung
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US11/560,031
• Publication Number:
  US 20070088968A1
• Time in Patent Office: 895 Days
• Field of Search: 713400-500, 713/503, 713/600
• US Class Current: 713/401
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0033 Correction by delay
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Claims

1. A system comprising:

a memory chip including an array of dynamic memory cells; and

a controller chip coupled to the memory chip, the controller chip including;

a first receiver to receive an incoming strobe signal provided by the memory chip;

a first transmitter to transmit an outgoing strobe signal to the memory chip;

a second transmitter to transmit data to the memory chip in response to a transmit clock signal;

a first register to store a value that represents a transmit phase to apply to the transmit clock signal, wherein the transmit phase is based on a detected phase of the outgoing strobe signal.

2. The system of claim 1, further comprising:

a locked loop circuit to generate a set of reference clock signals; and

a first mixer circuit, coupled to the locked loop circuit, to generate the transmit clock signal based on the value stored in the first register.

3. The system of claim 2, further comprising:

a second mixer to generate a tracking clock signal from the set of reference clock signals;

a phase detector to receive the outgoing strobe signal and compare the outgoing strobe signal to the tracking clock signal, the phase detector to generate a control signal based on phase shift detected between the outgoing strobe signal and the tracking clock signal by the phase detector;

a counter coupled to the phase detector, the counter to update a count value based on the control signal;

calibration logic, coupled to the first register, the calibration logic to calibrate the value that represents the transmit phase; and

monitor logic coupled to the counter, the monitor logic to issue indications to the calibration logic based on a change in the count value.

4. The system of claim 3, further comprising a signal line coupled to the memory chip and the controller chip, wherein the calibration logic calibrates the value to account for drift of a delay of a signal communicated between the memory chip and controller chip over the signal line.

5. The system of claim 1, further comprising:

a locked loop circuit to generate a set of reference clock signals;

a second receiver to receive data, provided by the memory chip, in response to a receive clock signal; and

a second mixer, coupled to the locked loop circuit, to generate the receive clock signal.

6. The system of claim 5, further comprising a second register to store a value that represents a receive phase to apply to the receive clock signal, wherein the receive phase is based on at least a detected phase of the outgoing strobe signal.

7. The system of claim 1, further comprising:

a first plurality of signal lines coupled to the memory chip and the controller chip, the controller chip to transmit address signals to the memory chip via the first plurality of signal lines; and

a second plurality of signal lines coupled to the memory chip and the controller chip, the controller chip to transmit control signals to the memory chip via the second plurality of signal lines.

8. The system of claim 1, wherein the memory chip is a double data rate dynamic random access memory device.

9. A method of operation in a system that includes a memory chip coupled to a controller chip, the method comprising:

transmitting an incoming strobe signal from the memory chip;

receiving the incoming strobe signal at a first receiver of the controller chip

transmitting an outgoing strobe signal from a transmitter of the controller chip to the memory chip;

transmitting data from a second transmitter of the controller chip, to the memory chip, in response to a transmit clock signal;

generating a transmit phase to apply to the transmit clock signal, wherein the transmit phase is based on at least a detected phase of the outgoing strobe signal.

10. The method of claim 9, further comprising:

storing a value indicating the transmit phase in a register;

generating a set of reference clock signals; and

mixing clock signals from the set of reference clock signals to derive the transmit clock signal, wherein the mixing is based on the value stored in the register.

11. The method of claim 10, further comprising:

generating a tracking clock signal from the set of reference clock signals;

comparing the outgoing strobe signal to the tracking clock signal to generate a control signal based on phase shift detected between the outgoing strobe signal and the tracking clock signal;

updating a counter value based the control signal; and

calibrating the value that represents the transmit phase based on changes.

12. The method of claim 11, wherein calibrating the value accounts for drift in a delay of a signal that is communicated between the controller chip and the memory chip.

13. The method of claim 9, further comprising:

receiving data, transmitted by the memory chip, at a second receiver of the controller chip in response to a receive clock signal; and

generating the receive clock signal from a set of reference clock signals; and

generating a receive phase to apply to the receive clock signal, wherein the receive phase is based on at least the detected phase of the outgoing strobe signal.

14. The method of claim 13, wherein generating the receive clock signal from the set of reference clock signals comprises mixing clock signals from the set of reference clock signals to derive the receive clock signal, wherein the mixing is based on a value stored in a register.

15. The method of claim 9, wherein the memory chip is a double data rate dynamic random access memory device.

16. A controller chip comprising:

a first receiver to receive an incoming strobe signal provided by a memory chip;

a first transmitter to transmit an outgoing strobe signal to the memory chip;

a second transmitter to transmit data to the memory chip in response to a transmit clock signal; and

a first register to store a value that represents a transmit phase to apply to the transmit clock signal, wherein the transmit phase is based on at least a detected phase of the outgoing strobe signal.

17. The controller chip of claim 16, further comprising:

a locked loop circuit to generate a set of reference clock signals; and

a first mixer circuit, coupled to the locked loop circuit, to generate the transmit clock signal based on the value stored in the first register.

18. The controller chip of claim 17, further comprising:

a second mixer circuit to generate a tracking clock signal from the set of reference clock signals;

a phase detector to receive the outgoing strobe signal and compare the outgoing strobe signal to the tracking clock signal, the phase detector to generate a control signal based on phase shift detected between the outgoing strobe signal and the tracking clock signal;

a counter coupled to the phase detector, the counter to update a count value based the control signal;

calibration logic, coupled to the first register, the calibration logic to calibrate the value that represents the transmit phase; and

monitor logic coupled to the counter, the monitor logic to issue indications to the calibration logic based on a change in the count value.

19. The controller chip of claim 16, further comprising:

a locked loop circuit to generate a set of reference clock signals;

a second receiver to receive data, provided by the memory chip, in response to a receive clock signal; and

a second mixer, coupled to the locked loop circuit, to generate the receive clock signal.

20. The controller chip of claim 19, further comprising a second register to store a value that represents a receive phase to apply to the receive clock signal, wherein the receive phase is based on at least the detected phase of the outgoing strobe signal.