Slave device having independent error recovery
First Claim
1. A slave device adapted to couple to a master processor, the slave device comprising:
- an error handler configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and configured to initiate and perform the selected error recovery operation; and
a communication controller configured to communicate with the master processor according to a master/slave protocol, the master/slave protocol comprising completion of a transaction that is on-going with the master processor when the error handler initiates the selected error recovery operation, the communication controller further configured to provide a reset interrupt signal to the master processor to notify the master processor that the error recovery operation has been completed, and to further notify the master processor that at least a portion of data transferred between the slave device and the master processor may have been lost or corrupted.
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Accused Products
Abstract
A slave device adapted to couple to a master processor and including an error handler and a communication controller. The error handler is configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and to initiate and perform the selected error recovery operation. The communication controller is configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.
63 Citations
24 Claims
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1. A slave device adapted to couple to a master processor, the slave device comprising:
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an error handler configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and configured to initiate and perform the selected error recovery operation; and a communication controller configured to communicate with the master processor according to a master/slave protocol, the master/slave protocol comprising completion of a transaction that is on-going with the master processor when the error handler initiates the selected error recovery operation, the communication controller further configured to provide a reset interrupt signal to the master processor to notify the master processor that the error recovery operation has been completed, and to further notify the master processor that at least a portion of data transferred between the slave device and the master processor may have been lost or corrupted. - View Dependent Claims (2, 3, 4, 5)
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6. A packet routing device configured as a slave to a master processor for routing data packets between the master processor and a network fabric, the packet routing device comprising:
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an error handler configured to detect errors internal to the packet routing device and, in response to detecting at least one error and independent of the master processor, configured to select and initiate an error recovery operation based on the at least one detected error, the error handler further configured to assert an error recovery flag that remains asserted until the error recovery operation is completed; and a communication controller configured to assert a transaction flag when a data transfer is taking place between the master processor and the packet routing device over a communication bus, the communication controller further configured to recognize the assertion of the error recovery flag yet complete the data transfer in order to avoid hanging the communication bus. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A memory device configured as a slave to a master processor, the memory device comprising:
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an error handler configured to detect errors internal to the memory device and, in response to detecting at least one error and independent of the master processor, configured to select and initiate an error recovery operation based on the at least one detected error, the error handler further configured to assert an error recovery flag upon initiation of the error recovery operation; a storage medium configured to store data; and a memory controller configured to assert a transaction flag when one of a write or a read operation is initiated upon the memory device for carrying out a data transfer between the master processor and the memory device over a communication bus, the communication controller further configured to recognize the assertion of the error recovery flag yet complete the data transfer in order to avoid hanging the communication bus. - View Dependent Claims (14, 15, 16, 17)
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18. A network system comprising:
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a master processor; and a slave device coupled to the master processor, the slave device comprising; an error handler configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detect error and configured to initiate and perform the selected error recovery operation; a communication controller configured to communicate with the master processor according to a master/slave protocol, and configured to complete an ongoing data transfer between the slave device and the master processor in spite of being aware of the error recovery operation; and the communication controller further configured to provide a reset interrupt signal to the master processor to notify the master processor that the error recovery operation has been completed. - View Dependent Claims (19, 20)
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21. A method of operating a slave device adapted to couple to a master processor, the method comprising:
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communicating with the master processor according to a master/slave protocol; detecting at least one error internal to the slave device; selecting an error recovery operation based on the at least one detected internal error; initiating and performing the selected error recovery operation independent of the master processor; completing at least one of a) a pending data transaction or b) an ongoing data transfer between the slave device and the master processor over a communication bus, regardless of a concurrent occurrence of the error recovery operation, in order to avoid disrupting the communication bus; and providing a reset interrupt signal to the master processor to notify the master processor that the error recovery operation has been completed. - View Dependent Claims (22, 23, 24)
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Specification